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    • High-order PLL design with constant phase margin 

      Ugarte Gil, Mikel Upna; Carlosena García, Alfonso Upna (IEEE, 2010)   Contribución a congreso / Biltzarrerako ekarpena  OpenAccess
      In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed ...