Now showing items 1-2 of 2

    • High-order PLL design with constant phase margin 

      Ugarte Gil, Mikel Upna; Carlosena García, Alfonso Upna (IEEE, 2010)   Contribución a congreso / Biltzarrerako ekarpena  OpenAccess
      In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed ...
    • Performance comparison and design guidelines for Type II and Type III PLLs 

      Ugarte Gil, Mikel Upna; Carlosena García, Alfonso Upna (Birkhauser, 2015)   Artículo / Artikulua  OpenAccess
      The advantages provided by Type III PLLs are poorly known, since these devices are very often considered unstable and difficult, or even impossible, to design. In this paper, a performance comparison between Type II and ...