High-order PLL design with constant phase margin
Ver/
Fecha
2010Versión
Acceso abierto / Sarbide irekia
Tipo
Contribución a congreso / Biltzarrerako ekarpena
Versión
Versión aceptada / Onetsi den bertsioa
Impacto
|
10.1109/MWSCAS.2010.5548890
Resumen
In this paper we describe a novel procedure to design
high-type high-order Phase Locked Loops (PLLs) from lower
order prototypes, preserving a prescribed Phase Margin (PM).
The method builds on a model recently proposed by the authors,
and is supported by extensive simulations and experimental
results, giving up to a type-III fifth-order PLL with a
commercial circuit. ...
[++]
In this paper we describe a novel procedure to design
high-type high-order Phase Locked Loops (PLLs) from lower
order prototypes, preserving a prescribed Phase Margin (PM).
The method builds on a model recently proposed by the authors,
and is supported by extensive simulations and experimental
results, giving up to a type-III fifth-order PLL with a
commercial circuit. [--]
Materias
High-order PLL design,
Constant phase margin
Editor
IEEE
Publicado en
2010 53rd IEEE International Midwest Symposium on Circuits and Systems. Seattle (Estados Unidos), 2010, pp. 570-573.
Departamento
Universidad Pública de Navarra. Departamento de Ingeniería Eléctrica y Electrónica /
Nafarroako Unibertsitate Publikoa. Ingeniaritza Elektrikoa eta Elektronikoa Saila
Versión del editor
Entidades Financiadoras
This work has been supported in part
by the Spanish Dirección General de Investigación and
FEDER under grants TEC2007-67460-C03/01 and DPI2007-
66615-C02-01.