Artículos de revista DIEC - IEKS Aldizkari artikuluak

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Browsing Artículos de revista DIEC - IEKS Aldizkari artikuluak by Department/Institute "Ingeniería Eléctrica y Electrónica"

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    PublicationOpen Access
    ±0.25 V Class-AB CMOS capacitance multiplier and precision rectifiers
    (IEEE, 2019) Pourashraf, Shirin; Ramírez-Angulo, Jaime; Hinojo Montero, José María; González Carvajal, Ramón; López Martín, Antonio; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
    Reduction of minimum supply requirements is a crucial aspect to decrease the power consumption in VLSI systems. A high performance capacitance multiplier able to operate with supplies as low as ±0.25 V is presented. It is based on adaptively biased class-AB current mirrors which provide high current efficiency. Measurement results of a factor 11 capacitance multiplier fabricated in 180 nm CMOS technology verify theoretical claims. Moreover, low-voltage precision rectifiers based on the same class-AB current mirrors are designed and fabricated in the same CMOS process. They generate output currents over 100 times larger than the quiescent current. Both proposed circuits have 300 nW static power dissipation when operating with ±0.25 V supplies.
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    PublicationOpen Access
    AC amplifiers with ultra-low corner frequency by using bootstrapping
    (Institution of Engineering and Technology, 2021) Martincorena Arraiza, Maite; Carlosena García, Alfonso; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Ingeniería Eléctrica y Electrónica; Institute of Smart Cities - ISC; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
    A novel architecture for an AC (i.e. high-pass) amplifier is proposed allowing a drastic reduction of the cutoff frequency to the sub-Hertz range. It builds upon the classic AC configuration with a high gain amplifier and a parallel RC circuit in the feedback loop, by increasing the feedback resistance through bootstrapping. Resistance multiplying factors higher than four orders of magnitude are easily achievable. The basic principle can be applied to several practical implementations, though in this letter it is demonstrate with measurement results of an op-amp based discrete implementation.
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    PublicationOpen Access
    Class AB amplifier with enhanced slew rate and GBW
    (John Wiley & Sons, 2019) Garde Luque, María Pilar; López Martín, Antonio; Algueta-Miguel, Jose M.; Ramírez-Angulo, Jaime; González Carvajal, Ramón; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
    The design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the Quasi-Floating Gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5 um CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.
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    PublicationOpen Access
    An enhanced gain-bandwidth class-AB miller op-amp with 23,800 MHz pF/mW FOM, 11-16 current efficiency and wide range of resistive and capacitive loads driving capability
    (IEEE, 2021) Paul, Anindita; Ramírez-Angulo, Jaime; Díaz Sánchez, Alejandro; López Martín, Antonio; González Carvajal, Ramón; Li, Frank X.; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica y Electrónica
    A compact power-efficient class-AB Miller op-amp is introduced. It uses a simple auxiliary circuit that enhances the op-amp's gain-bandwidth product and helps to drive a wide range of capacitive and resistive loads with high static and dynamic current efficiency. Simple Miller compensation is used to obtain stability over a wide range of loading conditions. The op-amp's simulation and experimental results in strong inversion with 15uA bias current and in sub-threshold with 250nA bias current are shown. Its performance is measured in terms of dynamic and static current efficiency figures of merit FOMCEDyn and FOMCEStat: and using the conventional small-signal figure of merit FOMSS: Experimental results of op-amps fabricated in a 130nm CMOS technology are shown that validate the proposed approach.
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    PublicationOpen Access
    Gain-boosted super class AB OTAs based on nested local feedback
    (IEEE, 2021) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica y Electrónica
    A new approach to design super class AB operational transcon-ductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOML) of 236 V-1. To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.
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    PublicationOpen Access
    Masked least-squares averaging in processing of scanning-EMG recordings with multiple-discharges
    (Springer, 2020) Corera Orzanco, Íñigo; Malanda Trigueros, Armando; Rodríguez Falces, Javier; Navallas Irujo, Javier; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    Removing artifacts from nearby motor units is one of the main objectives when processing scanning-EMG recordings. Methods such as median filtering or masked least-squares smoothing (MLSS) can be used to eliminate artifacts in recordings with just one discharge of the motor unit potential (MUP) at each location. However, more effective artifact removal can be achieved if several discharges per position are recorded. In this case, processing usually involves averaging the discharges available at each position and then applying a median filter in the spatial dimension. The main drawback of this approach is that the median filter tends to distort the signal waveform. In this paper, we present a new algorithm that operates on multiple discharges simultaneously and in the spatial dimension. We refer to this algorithm as the multi masked least-squares smoothing (MMLSS) algorithm: an extension of the MLSS algorithm for the case of multiple discharges. The algorithm is tested using simulated scanning-EMG signals in different recording conditions, i.e., at different levels of muscle contraction and for different numbers of discharges per position. Results demonstrate that the algorithm eliminates artifacts more effectively than any previously available method and does so without distorting the waveform of the signal.