Person:
Ugarte Gil, Mikel

Profile Picture

Email Address

person.page.identifierURI

https://academica-e.unavarra.es/handle/2454/50100

Birth Date

Research Projects

Organizational Units

Job Title

Last Name

Ugarte Gil

First Name

Mikel

person.page.departamento

Ingeniería Eléctrica y Electrónica

person.page.instituteName

ORCID

person.page.upna

9151

Name

Filters

20101
Reset filters

Settings

Subject: High-order PLL design ×

Search Results

Now showing 1 - 1 of 1
  • Thumbnail Image
    PublicationOpen Access
    High-order PLL design with constant phase margin
    (IEEE, 2010) Ugarte Gil, Mikel; Carlosena García, Alfonso; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed by the authors, and is supported by extensive simulations and experimental results, giving up to a type-III fifth-order PLL with a commercial circuit.