Person: López Martín, Antonio
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López Martín
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Antonio
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Ingeniería Eléctrica, Electrónica y de Comunicación
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ISC. Institute of Smart Cities
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0000-0001-7629-0305
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2254
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Publication Open Access AC coupled amplifier with a resistance multiplier technique for ultra-low frequency operation(Elsevier, 2022) Martincorena Arraiza, Maite; Cruz Blas, Carlos Aristóteles de la; Carlosena García, Alfonso; López Martín, Antonio; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación; Universidad Pública de Navarra / Nafarroako Unibertsitate PublikoaThis paper proposes a novel, tunable AC coupled capacitive feedback amplifier, exhibiting an ultra-low high pass corner frequency. This is accomplished by actively boosting the output resistive value of a MOS transistor in weak inversion. The circuit is based on a more general architecture, recently proposed by the authors, and is analyzed in terms of its capability to achieve ultra-low frequency operation, its DC performance, and noise. The proposed technique is demonstrated via measurement results from a fabricated test chip prototype using a standard 0.18 µm CMOS technology. The proposed amplifier provides a tunable high pass corner frequency from 20 mHz to 475 mHz, consuming 4.71 μW and a total area of 0.069 mm2.Publication Open Access Wide-swing class AB regulated cascode current mirror(IEEE, 2020) Garde Luque, María Pilar; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCA micropower regulated cascode CMOS current mirror is presented, combining floating gate and quasi floating gate MOS transistors to achieve both wide swing and class AB operation, respectively. Measurement results for a 0.5 μm CMOS test chip prototype are included, showing that the current mirror can provide a THD at 100 kHz of -44 dB for a supply voltage of ±0.75 V and input current amplitudes 20 times larger than the bias current.Publication Open Access Design of low-cost smart accelerometers(Universitat Politècnica de Catalunya, 2005) Carlosena García, Alfonso; López Martín, Antonio; Massarotto, Marco; Cruz Blas, Carlos Aristóteles de la; Lecumberri Villamediana, Pablo; Gómez Fernández, Marisol; Pintor Borobia, Jesús María; Gárriz Sanz, Sergio; Ingeniería Eléctrica y Electrónica; Matemáticas; Ingeniería Mecánica, Energética y de Materiales; Ingeniaritza Elektrikoa eta Elektronikoa; Matematika; Mekanika, Energetika eta Materialen IngeniaritzaThe goal of this project is to design a low-cost smart accelerometer, making use of a piezoelectric element as basic sensing material, and adding a mixed-mode conditioning circuit.Publication Open Access Low-power ultrasonic front-end for cargo container monitoring(IEEE, 2019) Algueta-Miguel, Jose M.; García Oya, José Ramón; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Muñoz Chavero, Fernando; Hidalgo Fort, Eduardo; Institute of Smart Cities - ISCA low-power ultrasonic communication system conceived for cargo container monitoring is presented. Two piezoelectric transducers operating at 40 kHz are used for generating and acquiring an ultrasonic signal through the metallic wall, thus establishing a non-invasive inside-outside communication that preserves the container integrity. Both transducers are fixed by means of a novel magnetic case designed for optimizing data transmission. The acoustic and electrical characteristics of the ultrasonic channel are analyzed. An experimental measurement setup based on FPGA has been implemented for comparing some basic modulation and detection schemes in terms of Bit Error Rate (BER), also considering their robustness against undesired mechanical and electromagnetic perturbations. On this basis, a compact digital DBPSK modulator using a square carrier signal is proposed. Frequency and amplitude tracking algorithms are designed for optimizing the quality and robustness of the data transmission. Finally, a low-power low-rate (up to few kbps) architecture based on the previous elements is presented. All the proposed contributions are experimentally validated.Publication Open Access Fault detection of planetary gears based on signal space constellations(MDPI, 2022) Martincorena Arraiza, Maite; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Molina Vicuña, Cristian; Matías Maestro, Ignacio; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de ComunicaciónA new method to process the vibration signal acquired by an accelerometer placed in a planetary gearbox housing is proposed, which is useful to detect potential faults. The method is based on the phenomenological model and consists of the projection of the healthy vibration signals onto an orthonormal basis. Low pass components representation and Gram–Schmidt’s method are conveniently used to obtain such a basis. Thus, the measured signals can be represented by a set of scalars that provide information on the gear state. If these scalars are within a predefined range, then the gear can be diagnosed as correct; in the opposite case, it will require further evaluation. The method is validated using measured vibration signals obtained from a laboratory test bench.Publication Open Access A 1.2-V current-mode RMS-to-DC converter based on a novel two-quadrant electronically simulated MOS translinear loop(IEEE, 2020) Martincorena Arraiza, Maite; Cruz Blas, Carlos Aristóteles de la; Algueta-Miguel, Jose M.; López Martín, Antonio; Institute of Smart Cities - ISCA novel current-mode CMOS RMS-to-DC converter using translinear techniques is introduced. It is based on a squarer/divider cell that is implemented using an electronically simulated loop with a novel biasing scheme that allows its operation in two quadrants. The cell is designed using a differential input current and a small signal first order filter to implement the voltage averaging, leading to a compact solution that can be used with low voltage supplies. The converter has been fabricated in a standard 130-nm CMOS process, and measurement results are provided to demonstrate the feasibility of the system.Publication Open Access Power-efficient single-stage class-AB OTA based on non-linear nested current mirrors(IEEE, 2023) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Institute of Smart Cities - ISCA novel approach to design low-power area-efficient rail-to-rail output single-stage class-AB operational transconductance amplifiers (OTAs) with enhanced large- and small-signal performance to drive large capacitive loads is presented. It is based on a non-linear nested current mirror at the active load of a splitted differential input pair biased in weak inversion that boosts dynamic currents beyond their quiescent value directly at the output branch. As a result, slew rate, DC gain, gainbandwidth product, settling time and noise performance are improved without additional circuit elements or power consumption. An OTA prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of 2.9 µW from a supply voltage of ±0.5 V and a silicon area of 0.001 mm2 . Measurement results validate the advantages of the proposal, exhibiting positive and negative slew rates of 110 V/ms and −58 V/ms, respectively, and a gain-bandwidth product of 136 kHz with a phase margin of 90◦ for a capacitive load of 160 pF.Publication Open Access Enhanced single-stage folded cascode OTA suitable for large capacitive loads(IEEE, 2018) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCAn enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gainbandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5-µm CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.Publication Open Access Micropower class AB low-pass analog filter based on the super-source follower(IEEE, 2022) Martincorena Arraiza, Maite; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Carlosena García, Alfonso; Institute of Smart Cities - ISCAn improved class AB version of the super source follower is used to implement a compact and power-efficient second order analog low-pass filter. The proposed circuit achieves a 41% power reduction as well as an improvement in linearity and pass band gain with respect to its class A counterpart. Measurement results of a test chip prototype fabricated in a 180 nm CMOS technology show a power consumption ranging from 50.3 μW to 85.27 μW for cutoff frequencies from 600 kHz to 890 kHz, with a supply voltage of ±0.75 V. A third order intermodulation distortion of −35.34 dB (for an input signal of 0.4 mV pp and 350 kHz) and a THD of −69.7 dB (for an input signal of 0.4 mV pp and 100 kHz) are measured, which results in an improvement with respect to the conventional class A version of 13.98 dB and 43.6 dB, respectively. The silicon area is 0.0592 mm 2 (using external capacitors).Publication Open Access Single-stage class-AB non-linear current mirror OTA(IEEE, 2022) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Institute of Smart Cities - ISCThe analysis, design and experimental characterization of a single-stage class-AB operational transconductance amplifier (OTA) with enhanced large- and small-signal performance is presented. The OTA is biased in weak inversion to save power and employs a non-linear current mirror as active load, leading a boosting current directly at the output branch. As a result, the amplifier's performance is improved without additional circuit elements and/or power consumption. A chip prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of 2.5 µW from a supply voltage of ±0.5 V and a silicon area of 0.0013 mm 2 . For a load of 160 pF, it exhibits an average slew rate of 0.94 V/µs and a gain-bandwidth product of 22.1 kHz.