Person: López Martín, Antonio
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López Martín
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Antonio
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Ingeniería Eléctrica, Electrónica y de Comunicación
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ISC. Institute of Smart Cities
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0000-0001-7629-0305
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2254
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Publication Open Access Super class AB RFC OTA using non-linear current mirrors(Institution of Engineering and Technology, 2018) Garde Luque, María Pilar; López Martín, Antonio; Carvajal, Ramón G.; Galán, J.A.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCAn alternative approach to the design of super class AB recycling folded cascode operational transconductance amplifiers is proposed. Instead of using local common-mode feedback for boosting dynamic currents, simple current mirrors with input transistors entering triode region for large currents are employed. Measurement results from a 0.5 μm CMOS test chip validate the proposal.Publication Open Access Wide-swing class AB regulated cascode current mirror(IEEE, 2020) Garde Luque, María Pilar; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCA micropower regulated cascode CMOS current mirror is presented, combining floating gate and quasi floating gate MOS transistors to achieve both wide swing and class AB operation, respectively. Measurement results for a 0.5 μm CMOS test chip prototype are included, showing that the current mirror can provide a THD at 100 kHz of -44 dB for a supply voltage of ±0.75 V and input current amplitudes 20 times larger than the bias current.Publication Open Access On the optimal current followers for wide-swing current-efficient amplifiers(IEEE, 2018) López Martín, Antonio; Garde Luque, María Pilar; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenThe design of various current followers for the implementation of OTAs with high slew rate and current efficiency is addressed. Two basic current follower topologies are compared, and modifications of both followers to improve these parameters are presented. As an application example, an enhanced recycling folded cascode OTA is proposed. Measurement results of the OTA fabricated in a 0.5 μm CMOS process show a 260% and 180% improvement in SR and GBW, respectively, for the same power consumption.Publication Open Access Folded Cascode OTA with 5540 MHzpF/mA FoM(IEEE, 2018) Garde Luque, María Pilar; López Martín, Antonio; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenA micropower single-stage folded cascode amplifier able to drive a wide range of capacitive loads is presented. It features class AB operation and includes power-efficient adaptive biasing techniques, which provide enhanced dynamic output current boosting and gain-bandwidth product (GBW). Phase lead compensation is used to improve phase margin and settling performance for low capacitive loads. Measurement results for a 0.5 μm CMOS process show a FoM of 5540 MHz pF/mA, the highest one reported to date for a folded cascode amplifier to the authors' knowledge.Publication Open Access Power efficient simple technique to convert a reset-and-hold into a true-sample-and-hold using an auxiliary output stage(IEEE, 2020) Rico-Aniles, Héctor Daniel; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Rocha-Pérez, José Miguel; Garde Luque, María Pilar; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenA technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%. The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the proposed technique.Publication Open Access Energy-efficient amplifiers based on quasi-floating gate techniques(MDPI, 2021) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Beloso Legarra, Javier; González Carvajal, Ramón; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de ComunicaciónEnergy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.Publication Open Access Super class AB RFC OTA with adaptive local common-mode feedback(Institution of Engineering and Technology, 2018) Garde Luque, María Pilar; López Martín, Antonio; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de ComunicaciónA super class AB recycling folded cascode operational transconductance amplifier is presented. It employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads. Measurement results from a test chip prototype fabricated in a 0.5 μm CMOS process validate the proposal.Publication Open Access Class AB amplifier with enhanced slew rate and GBW(John Wiley & Sons, 2019) Garde Luque, María Pilar; López Martín, Antonio; Algueta-Miguel, Jose M.; Ramírez-Angulo, Jaime; González Carvajal, Ramón; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenThe design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the Quasi-Floating Gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5 um CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.Publication Open Access 1-V 15-μW 130-nm CMOS super class AB OTA(IEEE, 2020) López Martín, Antonio; Algueta-Miguel, Jose M.; Garde Luque, María Pilar; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCA super class AB recycling folded cascode amplifier in 130 nm CMOS is presented. It combines for the first time adaptive biasing of the differential input pair, nonlinear current mirrors with current starving and dynamic biasing of the cascode transistors in the output branch. Measurements using a ±0.5V supply show slew rate and gain bandwidth product improvement factors of 26 and 112 versus the conventional topology for the same bias currents, yielding the highest combined FoM to date.Publication Open Access Enhanced single-stage folded cascode OTA suitable for large capacitive loads(IEEE, 2018) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCAn enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gainbandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5-µm CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.