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López Martín, Antonio

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https://academica-e.unavarra.es/handle/2454/49446

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López Martín

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Antonio

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Ingeniería Eléctrica, Electrónica y de Comunicación

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ISC. Institute of Smart Cities

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0000-0001-7629-0305

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2254

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Start date: 2000 × End date: 2009 × Author: López Martín, Antonio ×

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Now showing 1 - 4 of 4
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    PublicationOpen Access
    Design of low-cost smart accelerometers
    (Universitat Politècnica de Catalunya, 2005) Carlosena García, Alfonso; López Martín, Antonio; Massarotto, Marco; Cruz Blas, Carlos Aristóteles de la; Lecumberri Villamediana, Pablo; Gómez Fernández, Marisol; Pintor Borobia, Jesús María; Gárriz Sanz, Sergio; Ingeniería Eléctrica y Electrónica; Matemáticas; Ingeniería Mecánica, Energética y de Materiales; Ingeniaritza Elektrikoa eta Elektronikoa; Matematika; Mekanika, Energetika eta Materialen Ingeniaritza
    The goal of this project is to design a low-cost smart accelerometer, making use of a piezoelectric element as basic sensing material, and adding a mixed-mode conditioning circuit.
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    PublicationOpen Access
    Sensing in coin discriminators
    (IEEE, 2007) Carlosena García, Alfonso; López Martín, Antonio; Arizti, Fernando; Martínez de Guereñu, Ane; Pina Insausti, José L.; García Sayés, Miguel; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    This paper describes the technologies used in coin discriminator devices, stressing the improvements and novel mechanisms introduced by the authors in the past few years as a result of the cooperation with one leading company in the vending sector. Emphasis is put on how low-cost sensors are used to characterize coins (or tokens) and discriminate them from their counterfeits.
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    PublicationOpen Access
    A novel PLL architecture
    (2000) Osa, Juan I.; Carlosena García, Alfonso; López Martín, Antonio; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    A novel phase-locked loop scheme is proposed in this paper, whose main distinguishing features are infinite hold-in range, pull-out range fractionally constant and also a ripple fractionally constant. To this end, it incorporates a variable gain amplifer and a frequency tunable loop filter. The driving application is the on-chip automatic tuning of slave filters, although the PLL architecture can be employed in many other applications.
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    PublicationOpen Access
    Design of MOS-translinear multiplier/dividers in analog VLSI
    (Hindawi Publishing Corporation, 2000) López Martín, Antonio; Carlosena García, Alfonso; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/ divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-1am CMOS process, are provided in order to verify the correctness of the proposed approach.