Performance comparison and design guidelines for Type II and Type III PLLs
| dc.contributor.author | Ugarte Gil, Mikel | |
| dc.contributor.author | Carlosena García, Alfonso | |
| dc.contributor.department | Ingeniería Eléctrica y Electrónica | es_ES |
| dc.contributor.department | Ingeniaritza Elektrikoa eta Elektronikoa | eu |
| dc.date.accessioned | 2020-09-16T11:21:44Z | |
| dc.date.available | 2020-09-16T11:21:44Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | The advantages provided by Type III PLLs are poorly known, since these devices are very often considered unstable and difficult, or even impossible, to design. In this paper, a performance comparison between Type II and III PLLs is presented, based on an alternative model introduced by the authors. More precisely, the devices are exposed to chirp type and even more complex signals to demonstrate that Type III PLLs may offer better results in terms of phase margin and frequency response peaking when properly designed. As a result of our analysis, approximate closed form expressions will be proposed to evaluate Type III PLL performance and its relation to the parameters of the model. | en |
| dc.format.extent | 14 p. | |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.doi | 10.1007/s00034-015-0011-y | |
| dc.identifier.issn | 1531-5878 | |
| dc.identifier.uri | https://academica-e.unavarra.es/handle/2454/38099 | |
| dc.language.iso | eng | en |
| dc.publisher | Birkhauser | en |
| dc.relation.ispartof | Circuits, Systems, and Signal Processing, 2015, 34, 3395-3408 | en |
| dc.relation.publisherversion | https://doi.org/10.1007/s00034-015-0011-y | |
| dc.rights | © The Author(s) 2015. This article is distributed under the terms of the Creative Commons Attribution License which permits any use, distribution, and reproduction in any medium, provided the original author(s) and the source are credited. | en |
| dc.rights.accessRights | info:eu-repo/semantics/openAccess | |
| dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ | |
| dc.subject | Linear systems | en |
| dc.subject | PLLs | en |
| dc.subject | High-order PLLs | en |
| dc.subject | Type III | en |
| dc.subject | Type II | en |
| dc.subject | Loop filter | en |
| dc.title | Performance comparison and design guidelines for Type II and Type III PLLs | en |
| dc.type | info:eu-repo/semantics/article | |
| dc.type.version | info:eu-repo/semantics/publishedVersion | |
| dspace.entity.type | Publication | |
| relation.isAuthorOfPublication | 75eeeeb0-fc19-4492-941f-231f18cf8d37 | |
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| relation.isAuthorOfPublication.latestForDiscovery | 75eeeeb0-fc19-4492-941f-231f18cf8d37 |