López Martín, AntonioCarlosena García, Alfonso2017-02-102017-02-1020001065-514X (Print)1563-5171 (Electronic)https://academica-e.unavarra.es/handle/2454/23543A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/ divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-1am CMOS process, are provided in order to verify the correctness of the proposed approach.10 p.application/pdfeng© 2000 OPA (Overseas Publishers Association) N.V.Analog multiplier/dividersMultipliersMOS-translinearVoltage-translinearCMOS analog circuitsAnalog VLSIArtículo / ArtikuluaAcceso abierto / Sarbide irekiainfo:eu-repo/semantics/openAccess