López Martín, AntonioRico-Aniles, Héctor DanielRamírez-Angulo, JaimeRocha-Pérez, José MiguelGonzález Carvajal, Ramón2020-07-232020-07-2320202169-3536 (Electronic)10.1109/ACCESS.2020.2999315https://academica-e.unavarra.es/handle/2454/37369A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants. It operates with +/-0:45V supplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit FOMSS=5380 (MHz*pF/mW) and FOMLS=0:0085((V/ns)*pF/mA) for a nominal gain A=32.12 p.application/pdfengThis work is licensed under a Creative Commons Attribution 4.0 License.Low-voltageLow powerCMOS amplifiersTransresistance amplifierLinear transconductors.info:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccess