High-order PLL design with constant phase margin

Ugarte Gil, MikelCarlosena García, Alfonso2017-08-182017-08-182010M. Ugarte and A. Carlosena, "High-order PLL design with constant Phase Margin," 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, 2010, pp. 570-573. doi: 10.1109/MWSCAS.2010.5548890978-1-4244-7771-5 (Print)978-1-4244-7773-9 (Electronic)1548-3746 (Print)1558-3899 (Electronic)10.1109/MWSCAS.2010.5548890https://academica-e.unavarra.es/handle/2454/25230In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed by the authors, and is supported by extensive simulations and experimental results, giving up to a type-III fifth-order PLL with a commercial circuit.4 p.application/pdfengHigh-order PLL designConstant phase marginHigh-order PLL design with constant phase marginContribución a congreso / Biltzarrerako ekarpenaAcceso abierto / Sarbide irekiainfo:eu-repo/semantics/openAccess