Power efficient simple technique to convert a reset-and-hold into a true-sample-and-hold using an auxiliary output stage

Rico-Aniles, Héctor DanielRamírez-Angulo, JaimeLópez Martín, AntonioGonzález Carvajal, RamónRocha-Pérez, José MiguelGarde Luque, María Pilar2020-08-062020-08-062020H. D. Rico-Aniles, J. Ramírez-Angulo, A. J. Lopez-Martin, R. G. Carvajal, J. M. Rocha-Pérez and M. Pilar Garde, 'Power Efficient Simple Technique to Convert a Reset-and-Hold Into a True-Sample-and-Hold Using an Auxiliary Output Stage,' in IEEE Access, vol. 8, pp. 66508-66516, 2020, doi: 10.1109/ACCESS.2020.2985256.2169-353610.1109/ACCESS.2020.2985256https://academica-e.unavarra.es/handle/2454/37741A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%. The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the proposed technique.9 p.application/pdfengThis work is licensed under a Creative Commons Attribution 4.0 License.AmplifiersMixed-signal circuitsOffset compensationTrack-and-holdSample-andhold (S/H)Switched capacitorPower efficient simple technique to convert a reset-and-hold into a true-sample-and-hold using an auxiliary output stageinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/openAccess