Osa, Juan I.Carlosena García, AlfonsoLópez Martín, Antonio2017-02-102017-02-102000https://academica-e.unavarra.es/handle/2454/23549Trabajo presentado al XV Simposium Nacional de la Unión Científica de Radio (URSI '00), Zaragoza, 2000A novel phase-locked loop scheme is proposed in this paper, whose main distinguishing features are infinite hold-in range, pull-out range fractionally constant and also a ripple fractionally constant. To this end, it incorporates a variable gain amplifer and a frequency tunable loop filter. The driving application is the on-chip automatic tuning of slave filters, although the PLL architecture can be employed in many other applications.2 p.application/pdfengPhase-locked loop architectureinfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/openAccess