Pseudo-Three-Stage Miller Op-Amp With Enhanced Small-Signal and Large-Signal Performance

A simple technique to implement highly power efficient class AB–AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp’s effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has <inline-formula> <tex-math notation="LaTeX">$9~\text {V} \cdot \text {pF}/\mu \text {s}\cdot \mu \text{W}$ </tex-math></inline-formula> large-signal figure of merit (FOM) and <inline-formula> <tex-math notation="LaTeX">$17~\text {MHz}\cdot \text {pF}/\mu \text{W}$ </tex-math></inline-formula> small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has <inline-formula> <tex-math notation="LaTeX">$10~\text {V}\cdot \text {pF}/\mu \text {s}\cdot \mu \text{W}$ </tex-math></inline-formula> large-signal FOM and <inline-formula> <tex-math notation="LaTeX">$92~\text {MHz}\cdot \text {pF}/\mu \text{W}$ </tex-math></inline-formula> small-signal FOM with 0.5-V supply voltage.

Conventional high gain class-A two-stage Miller op-amp with telescopic input stage.
op-amp design is a challenging task for the analog designer in today's energy-constrained electronic world. Along with the low power and high speed, the op-amp must have a largesignal swing, high linearity, and high load driving capability. To achieve close to rail-to-rail output swing in low-voltage applications, a two-stage Miller op-amp is a wise choice. In this paper, a simple design approach of a Miller op-amp is presented to enhance gain-bandwidth product (GBW) by a large factor (63 times in the circuit presented here) and the dc open-loop gain by about one order of magnitude with just moderate increase (∼factor 2) in static power dissipation with respect to the conventional op-amp of Fig. 1. The approach also provides class AB operation to the input stage, improving the slew rate (SR). The efficiency of the op-amp is validated by measurements of a test chip and compared to other op-amps reported in the literature in terms of three figures of merit (FOMs): 1) the large-signal FOM LS = (SR.C L )/P Q , where P Q is the total static power dissipation and C L is the load capacitance; 2) the small-signal FOM SS = (GBW.C L )/P Q ; and 3) a global FOM FOM G = (FOM L S FOM S S ) 1/2 . In order to account for silicon area and total quiescent current (I TotalQ) , four additional FOM are also reported here: AFOMs = (SR.C L )/(P Q .Area), AFOM L = (GBW.C L )/(P Q .Area), IFOMs = (GBW.C L )/(I TotalQ) [4], and IFOM L = (SR.C L )/(I TotalQ ) [4].
This paper is organized as follows. Section II summarizes the limitations of a conventional two-stage class-A Miller op-amp. Section III describes the proposed op-amp designed in 130-nm CMOS technology operating in strong inversion with ±600-mV dual supplies and a bias current I B = 14 μA; and in subthreshold with ±250-mV supply voltages and a bias current I B = 70 nA. Section IV presents simulation results. Section V provides the experimental results of test chip prototypes of the proposed and conventional op-amps both in strong inversion and subthreshold. Conclusions are drawn in Section VI.

II. TWO-STAGE CLASS-A MILLER OP-AMP
A two-stage Miller op-amp with a telescopic input stage is shown in Fig. 1. This circuit can provide high openloop dc gain, A OLDC ∼ (g m r 0 ) 3 /4, where g m and r 0 are transconductance gain and output resistance of a unit size transistor, respectively. For simplicity, the parameters g m and r 0 are considered equal here for all unit size transistors. It also provides a moderate gain bandwidth product (GBW).The GBW of the class A op-amp of Fig. 1 can be obtained from its dc open-loop gain and the dominant pole at node X is given by the following equation: Here, R X = g m r 2 0 /2 is the impedance at node X and C X is the Miller capacitance given by the following equation: Here, A I I = g m r 0 /2 is the gain of the output stage.
As the dc open-loop gain of the op-amp is A OLDC = (g m r 0 ) 3 /4, the gain-bandwidth product is GBW cnv = g m /2πC C . The high-frequency pole f Pout at the output node of the op-amp is given by the following equation: Here, g mOUTP is the transconductance gain of the pMOS output transistor M OUTP and C L is the load capacitance. To achieve a high phase margin PM > 50 • when the zero introduced by C C is shifted to infinity (by selecting R C = 1/g mOUTP ), it is common to select C C = C L with transistors at the output stage scaled-up by a factor of 2. In this case, the GBW has a value GBW cnv = g m /2πC L and the highfrequency pole has a value f Pout = 2 GBW cnv .
Both GBW and f POut can be increased by a factor N by selecting C C = C L /N and scaling-up the output transistors by a factor 2N. Unfortunately, this increases the bias current and the quiescent power dissipation of the op-amp of Fig. 1 by a factor F = 0.4 (N + 1.5) and maintains the open-loop gain constant.
A drawback of this circuit is the asymmetrical slew rate. Though it can have a large positive slew rate (SR + ), its negative slew rate (SR − ) is constrained by the bias current of the output stage I OUTQ = 2I B . Hence, to improve SR − , it is required to increase I OUTQ which increases the static power dissipation. Slew rate (SR) can be enhanced without increasing static power dissipation by utilization of a class AB (push-pull) output stage. The SR of the input stage (given by SR inp = I inp /C C , where I inp = 2I B is the maximum current generated at node X by the input stage) can also limit the SR of the op-amp since the input stage has to provide current to the compensation capacitor C C at node X . For this reason, it is convenient that the op-amp has also a class AB input stage that can generate I inp > 2I B.
Though class AB operation can improve the current efficiency of the op-amp and decrease the linear part of the settling time, the exponential part of the settling time, determined by GBW, and phase margin (PM) can still lead to long total settling times in class AB op-amps. Hence to implement a high-speed op-amp both SR and GBW need to be improved simultaneously [5].
Power constraints in modern VLSI design demand an approach that can simultaneously increase GBW, SR, and open-loop gain. In Section III, an op-amp is proposed which can achieve large dc open-loop gain, enhanced GBW, and higher SR with just moderate increase in quiescent power. This op-amp can also work in subthreshold with little modification as shown in Section III-I. The small-signal and large-signal analysis for both op-amps are similar.

A. Operating Principle of the Proposed Op-Amp
The proposed Class AB-AB Miller op-amp is shown in Fig. 3. It is a pseudo-three-stage op-amp derived from the conventional class-A op-amp of Fig. 1 by replacing the input stage with a modified version of the cascoded current mirror OTA [6] shown in Fig. 2 and a free class AB [7] output stage. The diode-connected transistors M 2 , M 2P of the current mirror OTA are replaced by a resistive local common mode feedback (RLCMFB) load [8]. The second stage (M 3 -M 4 ) is a high gain fully cascoded amplifier (shown in blue). The combination of first and second stages is denoted as "composite input stage" (M 1 -M 4 ). It is framed by a blue dotted line in Fig. 3. The resistors R CM are selected so that the first stage (M 1 -M 2 shown in red and R CM ) of the composite input stage provides moderate gain and generates high-frequency poles ω P X at nodes X and X that have a negligible effect on the phase margin of the op-amp.
The output (third) stage (M OUTP and M OUTN ) is a push-pull amplifier with the free class-AB operation. The RLCMFB with two matched resistors (R CM ) in conjunction with the scaling of M 3 , M 4 by a factor 2 provides: 1) approximately one order of magnitude enhanced effective transconductance g meff , openloop gain, and higher GBW and 2) class AB operation at the op-amp's internal node Y. The output node of the composite input stage (node Y) has high output resistance R Y , and thus yields high gain. The output stage provides moderate gain, close to rail-to-rail output swing and class AB operation with comparably high positive and negative peak output currents. The class AB operation of both input and output stages of the op-amp prevents SR limitation of node Y by the bias current of the first stage. It results in high SR, and hence high FOM LS . The class AB output stage has the added advantage that it reduces the output impedance at high frequencies. This shifts the high-frequency output pole to higher frequencies, which improves the phase margin of the op-amp. The enhanced transconductance of the composite input stage g meff leads to essential improvement in GBW and in the dc open-loop gain. This results in much higher FOM SS and high phase margin, with just moderate additional power consumption as discussed in the following analysis.

B. Analysis of Class AB Operation of Input Stage
In this section, it is shown that besides high gain, the input stage of the proposed op-amp has class AB operation and can deliver currents to C C at node Y, which are larger than the static currents (2I B ) of transistors M 3 and M 4 . Under quiescent conditions, no current flows through the RLCMFB resistors R CM . Hence, M 2 -M 3 and M 2P−3P behave as conventional current mirrors at dc. The branch with M 3 in the second stage of the composite input stage is scaled up by a factor of 2 and has a quiescent current 2I B . In the presence of a differential input voltage V id, a signal current i = g m V id /2 flows through the R CM resistors and generates complementary voltage variations V X , V X across each R CM . The effective resistance at nodes X and X is R CM should be smaller than the output resistance of transistors M 1 , 2 , i.e., R CM << r o1,2 so that R X ≈ R CM . Complementary voltage variations with value V X = iR X appear at nodes X , X with maximum swing V X max = I B R X . The maximum source-gate voltage of transistors M 3 and M 3P is Transistor M 3 in the second stage can provide a maximum current I 3max at node Y which is given by the following equation: Defining M = (I B R X )/V SDsat3 , I 3max can be expressed by the following equation: Hence, depending on the value of R X and I B , resistors R CM can help to increase the positive and negative peak currents I peakY delivered to the compensation capacitor C C at node Y . Design values of R CM ≈ R X = 16 k, |V DSsat3 | = 160 mV, I B = 14 μA, and I B3Q = 2I B = 28 μA were selected here. These selections result in M+1 ≈ 2.4, which leads to a current I 3max = 6I B3Q = 12I B = 168μ A at node Y. Increasing R X results in higher M values (and higher gain), but this decreases the high-frequency poles at nodes X , X , and can lead to a reduction of the phase margin of the op-amp, as discussed in Section III-E.

C. Class AB Operation of Output Stage
To improve the SR, it is also necessary to increase the negative peak current of the output stage. This is done based on the free class AB technique [7]- [9] by means of a large resistance R Large and as mall capacitor C BAT that provides dynamic class AB operation at the output node of the op-amp. Under quiescent conditions, R Large provides equal bias voltage V BN to M TAIL and M OUTN , and consequently currents 2I B and N MOS I B flow through M TAIL and the two output transistors M OUTN and M OUTP , respectively. M OUTN is scaled by a factor N nMOS = 2N = 5 in the proposed design. This leads to a quiescent current I outQ = 5I B in the output branch transistors. Under dynamic conditions, when the op-amp is slewing in the negative direction, the voltage at node Y faces a positive change. Due to the presence of the large valued resistor, the capacitor cannot charge or discharge rapidly. Hence, it acts as a floating battery and transfers the voltage variations from node Y to node Z . Hence, a large dynamic negative current (higher than the quiescent output current N MOS I B ), can be obtained at the op-amp's output node, improving current efficiency CE = I omax /I TotalQ where I omax is the maximum output current and I TotalQ is the total op-amp's quiescent current.

D. Open-Loop-Gain Analysis of the Proposed Op-Amp
The simplified small-signal model of the proposed op-amp is shown in Fig. 4, leading to three poles: two at the internal nodes X and Y , and one at the output node. The feedforward path formed by R C and C C creates a zero. The corresponding open-loop transfer function A OL (s) of the proposed op-amp is expressed by the following equation: where A I , A I I , and A I I I are the dc gains of the first, second, and third stage, respectively. Gain Cascoded transistors M 3C and M 4C are used to increase the gain of the second stage A I I = g m3 R Y . R Y is expressed by the following equation assuming that all r o 's are equal and g m3 = g m4 = g m3C = g m4C : The resultant dc open-loop gain from the composite input stage is The output stage consists of a push-pull amplifier that provides moderate gain and close to rail-to-rail output swing. The dc gain of the output stage is A I I I = (g mOUTP )(r OUTP || r OUTN ).

E. Pole-Zero Analysis of the Proposed Op-Amp
Equation (8) shows that the op-amp has three poles and one zero. The selection of R CM plays an important role in this design, as it poses a tradeoff between the boosting of the gain A I = g m1 R X in the input stage, the value of the highfrequency poles (ω P X ) at node X (X ), and the peak current I 3max at node Y , as discussed in Section III-B. The pole of the circuit at node X , X is given by the following equation: Node C at the input stage operates with constant voltage (ac ground). Due to this, the effects of C GS2,2P are nullified at node X . Thus, the parasitic capacitance at node X is given by the following equation: Since C X is very small and R X r o , ω P X is a high-frequency pole( much higher than GBW), as shown later in Section III-G. In this case, its effect can be neglected, and A OL (s) of the opamp can be approximated by a conventional two-pole one-zero system and given by the following equation: The dominant pole at node Y is given approximately by the following equation: The GBW (in hertz) of the op-amp in Fig. 3 is given in the following equation: Equation (16) (14) corresponds to the output terminal and is given by the following equation: Here, g eff mOUT = g mOUTP + g mOUTN is the output conductance of the op-amp at high frequencies. The zero is given by the following equation: . Now, to achieve high GBW and high phase margin with low silicon area, C C is selected to have a moderate-low value C C = C L /10 and R C is selected so that the output pole ω POut matches the zero ω z . In this case, ω Pout and ω z can be lower than GBW, but the op-amp can still have high phase margin. This is discussed in detail in Section III-F with a design example.
The proposed approach enhances the open-loop gain and the effective g meff of the op-amp by providing an additional gain in the first stage with a negligible impact on the PM. This is possible in current technology (like in 0.13-μm CMOS technology and finer technologies) since the value of C X is very small. Thus, ω P X GBW. Hence, the enhancement of g meff improves GBW and the dc open-loop gain. On the contrary, using RLCMFB to enhance gain in previous technologies (like in 0.5-μm technology) [8], the value of C X was not so small and the poles at node X and X could be lower or close to GBW. So, in order to achieve a high PM phase, lead compensation was required. This uses a left half s plane zero generated by a resistor R s connected in series with C L to compensate for the phase shift of ω P X which can limit the op-amp's maximum dynamic output current. Thus, this proposed op-amp in 130-nm technology does not require phase lead compensation if the RLCMFB provides only moderate gain enhancement in the input stage.

F. Stability Analysis
As mentioned above [see (18)], in general for stability with PM > 50 • , the Miller op-amp is designed with R C = 1/g eff mOUT to shift the right half-s plane zero to infinity and the highfrequency output pole ω POut must be higher than GBW by at least a factor of 2. As indicated in Section II, a common practice to achieve this is to scale the output transistors by a factor 2 and to select C C = C L . In this case, the highfrequency output pole limits the maximum value of GBW to a value f POut /2 = g m /(2πC L ) = g m /(2πC C ). As discussed in Section II, GBW can be increased by a factor N by selecting C C = C L /N and scaling the output transistors by a factor of 2N. This increases quiescent power dissipation by a factor of 0.4(N + 1.5) and maintains the same dc open-loop gain.
The approach followed here allows to achieve higher GBW values with lower power dissipation as shown below. It consists of matching the value of the zero ω z to the output pole ω POut . From (17) and (18), the condition for pole-zero matching ω POut = ω z leads to R C = (1 + C L /C C )/g eff mOUT . Consider, for example, the design of the proposed circuit of Fig. 3 with scaling factors N pMOS = 2.5 and N nMOS = 5(I OUTQ = 5I B ) in the output stage transistors M OUTP and M OUTN , respectively, with C C = C L /10, R CM = 16 k, and a factor 2 scaling of transistor M 3 . The free class AB output stage can provide a g eff mOUT value given by the following equation: As The scaling of the output transistors shifts both the high-frequency output pole (and the matching zero) by almost an order of magnitude. Hence, this approach, in conjunction with the enhancement of g eff mOUT and the reduction of C C leads to an essentially higher GBW value than the conventional op-amp and places the output pole and zero at higher values, such that high PM is possible. Note that the enhancement of GBW is also possible due to the enhancement of g meff introduced by the RLCMFB and by the factor of 2 scaled-up transistors M 3 and M 3P in the composite input stage. In the proposed approach, a value GBW = A I g m3 /C C is obtained from (16) where A I ≈ 3.5 is the gain introduced by the RLCMFB in the first stage. Thus, g meff is enhanced by a factor of 2 A I ≈ 7. Variation of phase margin, unity-gain frequency, and pole-zero mismatch with R C.
Scaling down C C by a factor 10 provides additional GBW enhancement by the same factor. Hence GBW of the proposed circuit is given by GBW prop = 2 A I (g m /2πC c ) = 20 A I (g m /2πC L ) = 70 GBW cnv . This is a factor 70 times higher than the GBW of the conventional approach. This is achieved by: 1) enhancing g meff in three steps in the input stage; 2) scaling down C C ; and 3) matching the high-frequency pole to the high-frequency zero. Downscaling of capacitor C C also saves silicon area and simultaneously relaxes the SR requirements at the internal node Y of the composite input stage. Enhancing g meff also enhances the dc open-loop gain by a factor 2 A I . Fig. 5 shows the variation of the PM and pole-zero mismatch factor f z / f Pout as a function of R C obtained from simulations with C L = 50 pF. According to (18), the changes in R C lead to changes in ω z . It is desirable to have a high PM. From Fig. 5, it can be observed that the approach proposed here is robust against R C manufacturing variations since PM > 60 • for 2 k < R C < 2.8 k, which corresponds to a polezero mismatch range 0.93 < f Z / f Pout < 1.4. PM also remains higher than 55 • in the range from 1.5 k < R C < 3.3 k and 0.8 < f Z / f Pout < 1.9. It is noticeable that the phase margin is within 55 • for a large pole and zero mismatch factor between 0.7 and 1.9. Note that the accurate pole-zero matching is not required to achieve a high PM. However, pole-zero pairs (doublets) can affect the settling time(t Setl ) of class A and class AB op-amps [10]. According to [11], the exponential part of the transient response of the op-amp to a step input of amplitude V is given by the following equation: Here, ω z and ω p are pole and zero doublet frequencies. The third term can lead to long settling times if there is large relative pole-zero mismatch (ω z -ω p )/ GBW and/or low pole-zero doublet frequencies relative to GBW: ω z , ω p GBW. In the design proposed here, ω z and ω pOut are approximately a factor 4-5 lower than GBW. Simulations shown in Section IV-A with relatively large pole-zero mismatch values (ω z /ω pOut in the range from 0.8 to 1.7) caused by variations in R C and C L show that even in these large ranges the pole-zero mismatches do not lead to long settling times in the proposed design.
For f Z / f POut = 1 (pole matches the zero), (21) reduces to a one pole transfer function. In that case, the BW of the VF is f 3dBVF = GBW. Fig. 7 shows f 3dBVF / GBW as a function of mismatch f Z / f Pout . It can be noticed that for the range of 0.8 < f Z / f Pout < 1.32, f 3dBVF/GBW lies in the range of 0.8 < f 3dBVF/GBW < 1.22. Therefore, f 3dBVF is not highly sensitive to pole-zero mismatch. Table I shows the design parameters of the proposed design (column 2) and of the conventional op-amp of Fig. 1 for two cases: 1) with C C = C L and R C selected in such a way that f z is shifted to infinity (column 3) and 2) with C C = C L /10 and R C selected to achieve pole-zero cancellation (column 4). In the proposed design the nominal value of the zero f Z is 16 MHz obtained from (18)   C c = C L and f z shifted to infinity. In both cases, the GBWs are lower since the proposed g meff boosting technique is not used. The 0.1% positive and negative settling times (t + Setl and t − Setl ) of the proposed op-amp for the design parameters given in Table I are 45 and 50 ns, respectively, whereas for the Conv-A op-amp with C C = C L /10, t + Setl and t − Setl are 285 and 890 ns, respectively. For C C = C L , t + Setl and t − Setl are 1.2 and 2 μs, respectively.

H. Noise Analysis
The most significant sources of the internal noise in the opamp are the thermal noise of the MOSFETs and resistors and the flicker noise of the MOSFETs. A simple expression of the noise current spectral density of a MOSFET is [12] with T the absolute temperature, k B the Boltzmann's constant, μ the carrier mobility, K f the flicker noise coefficient, and γ a factor that varies from 1/2 to 2/3 from weak to strong inversion. The first term in (22) corresponds to thermal noise and the second term to flicker noise. The thermal noise of the resistor R CM can also be modeled by a current source with a power spectral density of I 2 nRCM ( f ) = 4 k B T /R CM . Fig. 8 shows the noise sources. Assuming that they are uncorrelated and that all transistors have the same γ factor, the inputreferred mean-square thermal noise of the amplifier in a bandwidth f is The noise contribution of the output stage is not considered as it is divided by the high-gain of the input-stage when referred to the input. Noting that g m3 = g m4 = 2g m2 and g m3 P = g m4 P = g m2 P = g m2 and g m1 = g m1 P , from (23) Note that for moderately large g m3 R CM and g m3P R CM noise is dominated by the first stage.
Regarding flicker noise, assuming as before uncorrelated noise sources and the same K f for all the transistors of the same type (nMOS or pMOS), the input-referred spectral noise density of the amplifier is As the same L was used for all the transistors (L = 180 nm in 130 nm technology), the flicker noise becomes Note that for the moderately large g m3 R CM and g m3P R CM , the expression corresponds to the well-known flicker noise of a simple differential pair, as the first stage dominates noise contribution. Note also that, in these conditions, noise is dominated by the input pair M 1 and M 1P , as K fn > K fp and μ n > μ p .

I. Subthreshold Op-Amp
The proposed op-amp can work in the subthreshold region with little modification. In the subthreshold region, quiescent power dissipation is lower as transistors can be biased with very low bias current (nAs) and with a supply voltage below 1 V. In biomedical applications and wireless sensor networks,  subthreshold op-amps are a good choice where high-speed is not a primary concern nevertheless a very low quiescent power dissipation is the foremost requirement. Fig. 9(a) shows a conventional Miller op-amp (without telescopic input stage) working in the subthreshold region. Fig. 9(b) shows a modified version of the proposed op-amp for operation in subthreshold. To avoid body effect and reduce the supply requirements in subthreshold, the substrates of the two pMOS cascode transistors (M 3CP and M 3C ) are connected to their source. In order to save the Silicon area, resistors used for local common mode feedback shown in Fig. 3 are replaced by MOS transistors operating in triode region with their gate connected to V SS . These transistors are designed to implement 1.5 M resistors in order to provide again A I close to as in the strong-inversion case. In Section IV, simulation results of the op-amps in strong-inversion and in subthreshold regions are discussed.

IV. SIMULATION RESULTS
The Proposed-AB-AB and conventional op-amps were designed in 130-nm CMOS technology with nMOS and pMOS

A. Simulation Results in Strong Inversion
The circuits of Figs. 1 and 3 were simulated with ±0.6-V dual supplies and bias current I B = 14μA. Fig. 10 shows its open-loop frequency response. It can be seen that the circuit of Fig. 1 (Conv-A)   Transient response shows settling time of Conv-A op-amp for C C = 50 pF and C C = 4.6 pF for 250-kHz pulse in strong inversion.     The class-A input stage of the Conv-A op-amp can deliver maximum positive and negative currents with value 2I B to the compensation capacitor C C at node X. The inclusion of a class-AB output stage does not lead to an improvement in the settling time as it is determined by the slew rate of the class-A input stage at node X. In addition, the much lower GBW value of the Conv-A op-amp also results in long exponential settling times in both directions. From Figs. 11 and 12, it can be observed that the inclusion of class-AB input and output stages enhances the dynamic output current in the Proposed-AB-AB op-amp. The Proposed-AB-AB op-amp has positive and negative output current enhancement factors 14 and 63, compared to the conventional op-amp. These results satisfy the theory of the proposed op-amp described in the previous section. To observe the effect of pole-zero doublet mismatches in the settling time Fig. 13 shows a transient response for R C in the range from 1.7 to 3.2 k. The 0.1% t Setl of the  op-amp is measured considering the time required for the response to reach and stay within a range of ±0.1% of the final value [13]. For a 1-MHZ 500 mV peak-to-peak amplitude step input the 0.1% positive settling time t + Setl varies from 28 to 66 ns and the negative settling time t − Setl varies from 35 to 70 ns for f z / f p mismatch factor within the range 1.67-0.8.  This is attributed to the higher dc gain and BW. To show the robustness of the proposed op-amp against process and temperature variations, corner analysis at three different temperatures for important performance parameters of the circuit are given in Table II. It can be asserted that proposed op-amp is robust against variation of process and temperature and can provide wide GBW. Standard deviation (SD) is shown in the table for each parameter for variation of the process for considered temperatures.

B. Simulation Results in Subthreshold Region
The proposed and conventional op-amps were also simulated in subthreshold with ±0.25-V supply voltage and bias current I B = 70 nA.   Fig. 18 shows that the Conv-A op-amp suffers from a poor settling time for the larger compensation capacitor. The Conv-A op-amp in subthreshold was fabricated with C C = 4.6 pF. Fig. 19 shows the transient output current of the proposed and conventional op-amps in subthreshold. The Proposed-AB-AB op-amp can provide maximum positive and negative output currents of 4.32 and 6.24 μA, respectively. Hence, the negative current limitation is significantly improved in the Proposed-AB-AB op-amp. The positive setting times of the Proposed-AB-AB and Conv-A op-amps are 3.2, and 12 μs, respectively, according to Fig. 20. The negative settling times of the Proposed-AB-AB and Conv-A-op-amps are 13 and 197 μs, respectively. Positive and negative PSRRs are 64 and 53 dB, respectively, whereas conventional op-amp has 50-and 47-dB positive and negative PSRRs. Fig. 21 shows the PSRR responses of the op-amps. Corner analysis of the proposed op-amp at different temperatures operating in the subthreshold region is given in Table III. It can be observed that the proposed op-amp is stable against the variation of process and temperature. The SD of each parameter for variation of the process has been given in Table III for the considered temperatures (0 • C, 27 • C, 100 • C).

V. EXPERIMENTAL RESULTS
Test chip prototypes of the proposed op-amps with C C = 4.6 pF and conventional op-amps with C C = 50 pF for strong inversion were fabricated in 130-nm CMOS process technology. For subthreshold operation, the proposed and Conv-A op-amps were fabricated with C C = 4.6 pF in 130-nm CMOS process also. The chips were tested with ±0.6-Vsupply voltage, quiescent current I TotalQ = 158 μA in strong inversion, ±0.25-V supply voltage and total quiescent current 0.78 μA in the subthreshold region. In both cases, the load capacitance C L is 50 pF.

A. Operation in Strong Inversion
The measured frequency response of the Conv-A and Proposed-AB-AB op-amps as voltage followers are shown in Fig. 22. The Proposed-AB-AB op-amp has a bandwidth of 57 MHz, whereas the Conv-A op-amp of Fig. 1 has a bandwidth of 1.1 MHz. Note that the bandwidth of the op-amp is improved by a factor of 52 compared to the conventional one. Transient responses of the op-amps are shown in Fig. 23 to   Fig. 24 for a ±600-mV, 1-MHz triangular input waveform. They have values of +600 and −384 mV for the proposed op-amp. Fig. 25 shows the chip micrograph of the proposed and conventional op-amps. Designed layouts are superimposed due to the opaque passivation layer. The silicon area consumed by the conventional op-amp is 0.07 mm 2 , whereas the area of the proposed op-amp is only 0.02 mm 2. Hence, in the proposed approach, higher large-and small-signal FOM can be obtained, while the silicon area can be essentially reduced because of smaller C C .  Fig. 27 shows the micrograph of the fabricated chip with the op-amps designed for subthreshold operation. The area occupied by the Proposed-AB-AB op-amp is 0.02 mm 2 which is two times more than the Conv-A op-amp designed in subthreshold. Though the proposed and conventional class-A op-amps are using similar compensation capacitor, the former occupied a larger area because the Proposed AB-AB opamp has an extra capacitor C BAT . The transient responses of conventional and proposed op-amps are given in Fig. 28 for a 20-kHz square waveform with 150-mV amplitude. The positive and negative SRs of the Proposed-AB-AB op-amp are 0.08 and 0.12 V/μs, whereas for Conv-A, they are 0.07 and 0.002 V/μs, respectively.

B. Operation in Subthreshold Region
Hence, the negative SR of the Conv-A op-amp is very poor. The maximum positive and negative output currents for the Proposed-AB-AB op-amp are 4.2 and 6.24 μA, while the Conv-A op-amp has maximum positive and negative current of 3.6 and 0.1 μA. The CE in subthreshold for the Proposed AB-AB op-amp is 6 and for Conv-A, it is 0.3. Hence, the proposed op-amp can achieve improved negative SR. Finally, the proposed op-amp can provide 12 times higher GBW, 62 times higher negative output current at the expense of increasing the quiescent power dissipation by a factor 2.6. The input/output common mode ranges for the Proposed-AB-AB op-amp are between 242 and -194.9 mV for ±250-mV 5-kHz triangular pulse, as shown in Fig. 29.
A comprehensive comparison of the proposed op-amp's performance with other state-of-the-art class-AB amplifiers is given in Table IV. From the table, it can be asserted that except the Si area related FOMs (strongly technology dependent), the Proposed-AB-AB op-amp has the highest small-signal, largesignal, and global FOM in strong inversion and subthreshold region. However, in strong inversion [18], it has 1.4 times higher IFOM L ; all other FOMs of it are lower.

VI. CONCLUSION
A power-efficient Miller op-amp architecture was reported and experimentally verified. Two versions of the op-amp were presented here: working in strong inversion as well as in subthreshold with little modification. These two versions were fabricated in 130-nm CMOS technology.
Experimental results verified that the proposed op-amp working with 1.2-V supply voltage has essentially improved large-and small-signal FOM LS = 9 and FOM SS = 17. The proposed op-amp operating in subthreshold also has the largest FOMs: FOM LS and FOM SS of 10 and 92, respectively. According to the literature presented in this paper, consequently, the highest value of the global FOM can be achieved which determines the ultimate speed of the proposed op-amp.
As in the subthreshold region, the op-amp can also operate with a very low supply voltage (±0.25 V); it can be used in applications where power constraints exist, such as in biomedical instruments and wireless sensor networks. Finally, it can be asserted that experimental results validated the proposed circuit's principle.