Buscar
Mostrando ítems 1-1 de 1
High-order PLL design with constant phase margin
(IEEE, 2010)
Contribución a congreso / Biltzarrerako ekarpena,
In this paper we describe a novel procedure to design
high-type high-order Phase Locked Loops (PLLs) from lower
order prototypes, preserving a prescribed Phase Margin (PM).
The method builds on a model recently proposed ...