Show simple item record

dc.contributor.advisorLópez Martín, Antonioes_ES
dc.creatorEsparza Alfaro, Fermínes_ES
dc.date.accessioned2015-03-10T10:21:36Z
dc.date.available2015-03-10T10:21:36Z
dc.date.issued2014
dc.date.submitted2014-11-27
dc.identifier.urihttps://hdl.handle.net/2454/16584
dc.description.abstractIn this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.es_ES
dc.format.extentXIII, 132 p.es_ES
dc.format.mimetypeapplication/pdfen
dc.language.isoengen
dc.relation.urihttps://biblioteca.unavarra.es/abnetopac/abnetcl.cgi?TITN=432721
dc.subjectAnalog circuitses_ES
dc.subjectLow voltagees_ES
dc.subjectLow poweres_ES
dc.subjectFloating-gate transistorses_ES
dc.subjectQuasi-floating-gate transistorses_ES
dc.titlePower-efficient current-mode analog circuits for highly integrated ultra low power wireless transceiverses_ES
dc.typeTesis doctoral / Doktoretza tesiaes
dc.typeinfo:eu-repo/semantics/doctoralThesisen
dc.contributor.departmentUniversidad Pública de Navarra. Departamento de Ingeniería Eléctrica y Electrónicaes_ES
dc.contributor.departmentNafarroako Unibertsitate Publikoa. Ingeniaritza Elektriko eta Elektronikoa Sailaeu
dc.rights.accessRightsinfo:eu-repo/semantics/openAccessen
dc.rights.accessRightsAcceso abierto / Sarbide irekiaes
dc.description.doctorateProgramPrograma Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)es_ES
dc.description.doctorateProgramKomunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007)eu


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record