Design of MOS-translinear multiplier/dividers in analog VLSI
Fecha
2000Versión
Acceso abierto / Sarbide irekia
Tipo
Artículo / Artikulua
Versión
Versión publicada / Argitaratu den bertsioa
Impacto
|
nodoi-noplumx
|
Resumen
A general framework for designing current-mode CMOS analog multiplier/divider
circuits based on the cascade connection of a geometric-mean circuit and a squarer/
divider is presented. It is shown how both building blocks can be readily obtained from
a generic second-order MOS translinear loop. Various implementations are proposed,
featuring simplicity, favorable precision and wide dynamic ran ...
[++]
A general framework for designing current-mode CMOS analog multiplier/divider
circuits based on the cascade connection of a geometric-mean circuit and a squarer/
divider is presented. It is shown how both building blocks can be readily obtained from
a generic second-order MOS translinear loop. Various implementations are proposed,
featuring simplicity, favorable precision and wide dynamic range. They can be successfully
employed in a wide range of analog VLSI processing tasks. Experimental
results of two versions, based on stacked and folded MOS-translinear loops and fabricated
in a 2.4-1am CMOS process, are provided in order to verify the correctness of
the proposed approach. [--]
Materias
Analog multiplier/dividers,
Multipliers,
MOS-translinear,
Voltage-translinear,
CMOS analog circuits,
Analog VLSI
Editor
Hindawi Publishing Corporation
Publicado en
VLSI Design, 2000, Vol. 11, No. 4, pp. 321-329
Departamento
Universidad Pública de Navarra. Departamento de Ingeniería Eléctrica y Electrónica /
Nafarroako Unibertsitate Publikoa. Ingeniaritza Elektrikoa eta Elektronikoa Saila
Entidades Financiadoras
Financial support from the CICYT under grant
(TIC 97/0418-C02-01) and the Gobierno de
Navarra are gratefully acknowledged.