Mostrar el registro sencillo del ítem
A novel PLL architecture
| dc.creator | Osa, Juan I. | es_ES |
| dc.creator | Carlosena García, Alfonso | es_ES |
| dc.creator | López Martín, Antonio | es_ES |
| dc.date.accessioned | 2017-02-10T09:41:44Z | |
| dc.date.available | 2017-02-10T09:41:44Z | |
| dc.date.issued | 2000 | |
| dc.identifier.uri | https://hdl.handle.net/2454/23549 | |
| dc.description | Trabajo presentado al XV Simposium Nacional de la Unión Científica de Radio (URSI '00), Zaragoza, 2000 | es_ES |
| dc.description.abstract | A novel phase-locked loop scheme is proposed in this paper, whose main distinguishing features are infinite hold-in range, pull-out range fractionally constant and also a ripple fractionally constant. To this end, it incorporates a variable gain amplifer and a frequency tunable loop filter. The driving application is the on-chip automatic tuning of slave filters, although the PLL architecture can be employed in many other applications. | en |
| dc.description.sponsorship | This work has been suported by the CICYT under grant TIC 97-418-C02-01. | en |
| dc.format.extent | 2 p. | |
| dc.format.mimetype | application/pdf | en |
| dc.language.iso | eng | en |
| dc.subject | Phase-locked loop architecture | en |
| dc.title | A novel PLL architecture | en |
| dc.type | Contribución a congreso / Biltzarrerako ekarpena | es |
| dc.type | info:eu-repo/semantics/conferenceObject | en |
| dc.contributor.department | Ingeniería Eléctrica y Electrónica | es_ES |
| dc.contributor.department | Ingeniaritza Elektrikoa eta Elektronikoa | eu |
| dc.rights.accessRights | Acceso abierto / Sarbide irekia | es |
| dc.rights.accessRights | info:eu-repo/semantics/openAccess | en |
| dc.type.version | Versión publicada / Argitaratu den bertsioa | es |
| dc.type.version | info:eu-repo/semantics/publishedVersion | en |
