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Design of MOS-translinear multiplier/dividers in analog VLSI
(Hindawi Publishing Corporation, 2000)
Artículo / Artikulua,
A general framework for designing current-mode CMOS analog multiplier/divider
circuits based on the cascade connection of a geometric-mean circuit and a squarer/
divider is presented. It is shown how both building blocks ...
A novel PLL architecture
(2000)
Contribución a congreso / Biltzarrerako ekarpena,
A novel phase-locked loop scheme is
proposed in this paper, whose main distinguishing
features are infinite hold-in range, pull-out range
fractionally constant and also a ripple fractionally
constant. To this end, it ...