Cruz Blas, Carlos Aristóteles de la
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Cruz Blas
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Carlos Aristóteles de la
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Ingeniería Eléctrica, Electrónica y de Comunicación
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ISC. Institute of Smart Cities
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27 results
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Publication Open Access Power-efficient single-stage class-AB OTA based on non-linear nested current mirrors(IEEE, 2023) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Institute of Smart Cities - ISCA novel approach to design low-power area-efficient rail-to-rail output single-stage class-AB operational transconductance amplifiers (OTAs) with enhanced large- and small-signal performance to drive large capacitive loads is presented. It is based on a non-linear nested current mirror at the active load of a splitted differential input pair biased in weak inversion that boosts dynamic currents beyond their quiescent value directly at the output branch. As a result, slew rate, DC gain, gainbandwidth product, settling time and noise performance are improved without additional circuit elements or power consumption. An OTA prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of 2.9 µW from a supply voltage of ±0.5 V and a silicon area of 0.001 mm2 . Measurement results validate the advantages of the proposal, exhibiting positive and negative slew rates of 110 V/ms and −58 V/ms, respectively, and a gain-bandwidth product of 136 kHz with a phase margin of 90◦ for a capacitive load of 160 pF.Publication Open Access Electromagnetic vibrational harvester based on U-shaped ferromagnetic cantilever: a novel two-magnet configuration(Elsevier, 2024-09-07) Gandía Aguado, David; Garayo Urabayen, Eneko; Beato López, Juan Jesús; Royo Silvestre, Isaac; Cruz Blas, Carlos Aristóteles de la; Tainta Ausejo, Santiago; Gómez Polo, Cristina; Ciencias; Zientziak; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoa eta Telekomunikazio Ingeniaritza; Estadística, Informática y Matemáticas; Estatistika, Informatika eta Matematika; Institute for Advanced Materials and Mathematics - INAMAT2; Institute of Smart Cities - ISCElectromagnetic vibrational harvesters are low-cost devices featuring high-power densities and robust structures, often used for capturing the energy of environmental vibrations (civil infrastructures, transportation, human motion, etc.,). Based on Faraday's law, energy generation relies on the modification of the magnetic field distribution within a magnetic element caused by mechanical vibrations inducing an electromotive force (EMF) in a pick-up coil. However, the practical implementation of this type of vibrational harvester is currently limited due to the reduced generated power under low-frequency vibrations. In this work, an electromagnetic vibrational harvester is experimentally characterized and analyzed employing magnetic circuit analysis. The harvester consists of a ferromagnetic U-shaped cantilever, a NdFeB magnet and a ferrite magnet used as ¿magnetic tip mass¿ to enhance the magnetic flux changes under vibrations of frequency < 100 Hz. For this configuration, an experimental voltage of ¿ 1.2 V peak-to-peak (open circuit) was obtained at a resonant frequency of 77 Hz, enabling the subsequent electronic rectification stage. Additionally, Finite Element Method (FEM) is used to explore different design possibilities including the modeling of complex geometries, mechanical properties and non-linear magnetic materials, enabling the tuning of the resonance frequency from 51 to 77 Hz, keeping constant the induced voltage.Publication Open Access Design of low-cost smart accelerometers(Universitat Politècnica de Catalunya, 2005) Carlosena García, Alfonso; López Martín, Antonio; Massarotto, Marco; Cruz Blas, Carlos Aristóteles de la; Lecumberri Villamediana, Pablo; Gómez Fernández, Marisol; Pintor Borobia, Jesús María; Gárriz Sanz, Sergio; Ingeniería Eléctrica y Electrónica; Matemáticas; Ingeniería Mecánica, Energética y de Materiales; Ingeniaritza Elektrikoa eta Elektronikoa; Matematika; Mekanika, Energetika eta Materialen IngeniaritzaThe goal of this project is to design a low-cost smart accelerometer, making use of a piezoelectric element as basic sensing material, and adding a mixed-mode conditioning circuit.Publication Open Access AC coupled amplifier with a resistance multiplier technique for ultra-low frequency operation(Elsevier, 2022) Martincorena Arraiza, Maite; Cruz Blas, Carlos Aristóteles de la; Carlosena García, Alfonso; López Martín, Antonio; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación; Universidad Pública de Navarra / Nafarroako Unibertsitate PublikoaThis paper proposes a novel, tunable AC coupled capacitive feedback amplifier, exhibiting an ultra-low high pass corner frequency. This is accomplished by actively boosting the output resistive value of a MOS transistor in weak inversion. The circuit is based on a more general architecture, recently proposed by the authors, and is analyzed in terms of its capability to achieve ultra-low frequency operation, its DC performance, and noise. The proposed technique is demonstrated via measurement results from a fabricated test chip prototype using a standard 0.18 µm CMOS technology. The proposed amplifier provides a tunable high pass corner frequency from 20 mHz to 475 mHz, consuming 4.71 μW and a total area of 0.069 mm2.Publication Open Access Bulk-driven CMOS linear transconductance-cell for AC amplifiers with very low cut-off frequency(Elsevier, 2023) Ocampo-Hidalgo, Juan J.; Domínguez, Miguel Á.; Cruz Blas, Carlos Aristóteles de la; Carrillo, Juan M.; Ingeniería Eléctrica, Electrónica y de Comunicación; Institute of Smart Cities - ISC; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenThis manuscript proposes a novel linearized transconductor for AC amplifiers with a very low cut-off frequency. The cell uses an alternative solution that is based on a modified source-degeneration OTA, using two bulkdriven buffers, incorporating bootstrapping techniques to a buffer and a degenerated resistor. In the buffer, the bootstrapping effect is implemented by using a pseudo-resistor and a linear capacitor properly configured, whereas in the resistor the output voltages of the buffers are used with this goal. Thus, the proposed solution allows realizing a very large time constant, avoiding the use of very large size resistors and capacitors, thus saving chip area. The technique is demonstrated in an 0.18 μm CMOS technology by designing an OTA operating with a supply voltage of 0.6 V and achieving a low cut-off frequency of around 2 Hz with a power consumption of 462 nW.Publication Open Access Gain-boosted super class AB OTAs based on nested local feedback(IEEE, 2021) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica y ElectrónicaA new approach to design super class AB operational transcon-ductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOML) of 236 V-1. To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.Publication Open Access Enhanced single-stage folded cascode OTA suitable for large capacitive loads(IEEE, 2018) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCAn enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gainbandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5-µm CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.Publication Open Access Wide-swing class AB regulated cascode current mirror(IEEE, 2020) Garde Luque, María Pilar; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCA micropower regulated cascode CMOS current mirror is presented, combining floating gate and quasi floating gate MOS transistors to achieve both wide swing and class AB operation, respectively. Measurement results for a 0.5 μm CMOS test chip prototype are included, showing that the current mirror can provide a THD at 100 kHz of -44 dB for a supply voltage of ±0.75 V and input current amplitudes 20 times larger than the bias current.Publication Open Access Low-power wide-bandwidth CMOS indirect current feedback instrumentation amplifier(Elsevier, 2020) Carrillo, Juan M.; Domínguez, Miguel Á.; Pérez Aloe, Raquel; Cruz Blas, Carlos Aristóteles de la; Duque Carrillo, J. Francisco; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenThe analysis and design trade-offs of a simple and economical technique to implement wideband low-voltage CMOS instrumentation amplifiers (IAs) based on indirect current feedback (ICF), are described. The input and an output transconductors consist of two super-source-followers and a resistor. As a result, the overall performance of the IA is enhanced. A thorough analysis of the proposed technique provided valuable insight on its operation. Two different realizations in 0.35-μm CMOS technology of an IA operating with a supply voltage of 3 V, are presented. In particular, a wide bandwidth single-stage IA with fixed voltage gain equal to 50 V/V and a low-power two-stage IA with externally programmable voltage gain, have been designed and characterized by extensive simulations. The simulated results of both circuits showed an improved response in terms of bandwidth, noise and power consumption, while their overall performance is comparable to other proposed approaches in terms of common-mode rejection ratio (CMRR) and linearity (THD).Publication Open Access Low-power ultrasonic front-end for cargo container monitoring(IEEE, 2019) Algueta-Miguel, Jose M.; García Oya, José Ramón; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Muñoz Chavero, Fernando; Hidalgo Fort, Eduardo; Institute of Smart Cities - ISCA low-power ultrasonic communication system conceived for cargo container monitoring is presented. Two piezoelectric transducers operating at 40 kHz are used for generating and acquiring an ultrasonic signal through the metallic wall, thus establishing a non-invasive inside-outside communication that preserves the container integrity. Both transducers are fixed by means of a novel magnetic case designed for optimizing data transmission. The acoustic and electrical characteristics of the ultrasonic channel are analyzed. An experimental measurement setup based on FPGA has been implemented for comparing some basic modulation and detection schemes in terms of Bit Error Rate (BER), also considering their robustness against undesired mechanical and electromagnetic perturbations. On this basis, a compact digital DBPSK modulator using a square carrier signal is proposed. Frequency and amplitude tracking algorithms are designed for optimizing the quality and robustness of the data transmission. Finally, a low-power low-rate (up to few kbps) architecture based on the previous elements is presented. All the proposed contributions are experimentally validated.
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