Carlosena García, Alfonso

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https://academica-e.unavarra.es/handle/2454/48803

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Carlosena García

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Alfonso

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Ingeniería Eléctrica, Electrónica y de Comunicación

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ISC. Institute of Smart Cities

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0000-0002-7146-4043

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88403

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370

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End date: 2018 × Subject: Analog multiplier/dividers ×

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    PublicationOpen Access
    Design of MOS-translinear multiplier/dividers in analog VLSI
    (Hindawi Publishing Corporation, 2000) López Martín, Antonio; Carlosena García, Alfonso; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/ divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-1am CMOS process, are provided in order to verify the correctness of the proposed approach.