(IEEE, 2010) Ugarte Gil, Mikel; Carlosena García, Alfonso; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
In this paper we describe a novel procedure to design
high-type high-order Phase Locked Loops (PLLs) from lower
order prototypes, preserving a prescribed Phase Margin (PM).
The method builds on a model recently proposed by the authors,
and is supported by extensive simulations and experimental
results, giving up to a type-III fifth-order PLL with a
commercial circuit.
