High-order PLL design with constant phase margin
Date
2010
Director
Publisher
IEEE
Acceso abierto / Sarbide irekia
Contribución a congreso / Biltzarrerako ekarpena
Versión aceptada / Onetsi den bertsioa
Project identifier
Impacto
No disponible en Scopus
Abstract
In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed by the authors, and is supported by extensive simulations and experimental results, giving up to a type-III fifth-order PLL with a commercial circuit.
Description
Keywords
High-order PLL design, Constant phase margin
Department
Ingeniería Eléctrica y Electrónica / Ingeniaritza Elektrikoa eta Elektronikoa
Faculty/School
Degree
Doctorate program
item.page.cita
M. Ugarte and A. Carlosena, "High-order PLL design with constant Phase Margin," 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, 2010, pp. 570-573.
doi: 10.1109/MWSCAS.2010.5548890
item.page.rights
Los documentos de Academica-e están protegidos por derechos de autor con todos los derechos reservados, a no ser que se indique lo contrario.