López Martín, Antonio
Loading...
Email Address
person.page.identifierURI
Birth Date
Job Title
Last Name
López Martín
First Name
Antonio
person.page.departamento
Ingeniería Eléctrica, Electrónica y de Comunicación
person.page.instituteName
ISC. Institute of Smart Cities
ORCID
person.page.observainves
person.page.upna
Name
- Publications
- item.page.relationships.isAdvisorOfPublication
- item.page.relationships.isAdvisorTFEOfPublication
- item.page.relationships.isAuthorMDOfPublication
45 results
Search Results
Now showing 1 - 10 of 45
Publication Open Access Super-gain-boosted miller op-amp based on nested regulated cascode techniques with FoMAOLDC =24,614kV/V.MHz.pF/µWatt(IEEE, 2020) Paul, Anindita; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Díaz Sánchez, Alejandro; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenA simple technique to greatly enhance the DC open-loop gain of a Miller op-amp is introduced here. It is based on the utilization of nested regulated cascode amplifiers. It uses conventional Miller compensation and does not increase the supply voltage. The proposed scheme has a DC open-loop gain Figure of Merit FoMAOLDC=24,614kV/V.pF.MHz/µWatt. It is especially appropriate for utilization in modern deep sub-micrometer CMOS technologies with low intrinsic gain.Publication Open Access A highly efficient composite class-AB–AB Miller op-amp with high gain and stable from 15 pF up to very large capacitive loads(IEEE, 2018) Pourashraf, Shirin; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenIn this paper, a highly power-efficient class-AB–AB Miller op-amp is discussed. The structure uses gm enhancement based on local common-mode feedback to provide class-AB operation with enhanced effective gm , open-loop gain, unity-gain frequency, and slew rate ( SR ) without significant increase in quiescent power consumption. Utilization of a nonlinear load leads to large symmetric positive and negative SRs . Stability over an extremely wide range of capacitive loads is achieved through a combination of Miller and phase-lead compensations. The unity-gain frequency does not show sensitivity to capacitive load values. A test chip prototype fabricated in 0.18- μm CMOS technology shows 90.8-dB open-loop gain, 12.5-MHz bandwidth for a 25-pF load capacitance, and a factor 60 SR enhancement with maximum output current close to 1-mA and 43- μA total static current.Publication Open Access Folded Cascode OTA with 5540 MHzpF/mA FoM(IEEE, 2018) Garde Luque, María Pilar; López Martín, Antonio; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenA micropower single-stage folded cascode amplifier able to drive a wide range of capacitive loads is presented. It features class AB operation and includes power-efficient adaptive biasing techniques, which provide enhanced dynamic output current boosting and gain-bandwidth product (GBW). Phase lead compensation is used to improve phase margin and settling performance for low capacitive loads. Measurement results for a 0.5 μm CMOS process show a FoM of 5540 MHz pF/mA, the highest one reported to date for a folded cascode amplifier to the authors' knowledge.Publication Open Access Class AB amplifier with enhanced slew rate and GBW(John Wiley & Sons, 2019) Garde Luque, María Pilar; López Martín, Antonio; Algueta-Miguel, Jose M.; Ramírez-Angulo, Jaime; González Carvajal, Ramón; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenThe design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the Quasi-Floating Gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5 um CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.Publication Open Access 1-V 15-μW 130-nm CMOS super class AB OTA(IEEE, 2020) López Martín, Antonio; Algueta-Miguel, Jose M.; Garde Luque, María Pilar; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCA super class AB recycling folded cascode amplifier in 130 nm CMOS is presented. It combines for the first time adaptive biasing of the differential input pair, nonlinear current mirrors with current starving and dynamic biasing of the cascode transistors in the output branch. Measurements using a ±0.5V supply show slew rate and gain bandwidth product improvement factors of 26 and 112 versus the conventional topology for the same bias currents, yielding the highest combined FoM to date.Publication Open Access Design of low-cost smart accelerometers(Universitat Politècnica de Catalunya, 2005) Carlosena García, Alfonso; López Martín, Antonio; Massarotto, Marco; Cruz Blas, Carlos Aristóteles de la; Lecumberri Villamediana, Pablo; Gómez Fernández, Marisol; Pintor Borobia, Jesús María; Gárriz Sanz, Sergio; Ingeniería Eléctrica y Electrónica; Matemáticas; Ingeniería Mecánica, Energética y de Materiales; Ingeniaritza Elektrikoa eta Elektronikoa; Matematika; Mekanika, Energetika eta Materialen IngeniaritzaThe goal of this project is to design a low-cost smart accelerometer, making use of a piezoelectric element as basic sensing material, and adding a mixed-mode conditioning circuit.Publication Open Access Sensing in coin discriminators(IEEE, 2007) Carlosena García, Alfonso; López Martín, Antonio; Arizti, Fernando; Martínez de Guereñu, Ane; Pina Insausti, José L.; García Sayés, Miguel; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta ElektronikoaThis paper describes the technologies used in coin discriminator devices, stressing the improvements and novel mechanisms introduced by the authors in the past few years as a result of the cooperation with one leading company in the vending sector. Emphasis is put on how low-cost sensors are used to characterize coins (or tokens) and discriminate them from their counterfeits.Publication Open Access Energy harvesting approaches in IoT scenarios with very low ambient energy(European Association for the Development of Renewable Energy, Environment and Power Quality (EA4EPQ), 2019) López Martín, Antonio; Algueta-Miguel, Jose M.; Matías Maestro, Ignacio; Institute of Smart Cities - ISCThe feasibility of multi-source energy harvesting in Internet of Things (IoT) scenarios with low and intermittent ambient energy is addressed. As a relevant case study, application to a smart cargo container system is analysed. The most relevant features of the main energy sources available in this target application are identified, and various transducers adapted to such sources are evaluated. Measurement results indicate that combined piezoelectric and thermoelectric generation inside cargo containers can significantly extend the battery lifetime of IoT end nodes embedded in such containers.Publication Open Access Pseudo-three-stage Miller op-amp with enhanced small-signal and large-signal performance(IEEE, 2019) Paul, Anindita; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Rocha-Pérez, José Miguel; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de ComunicaciónA simple technique to implement highly power efficient class AB-AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp's effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has 9 V·pF/μs·μW large-signal figure of merit (FOM) and 17 MHz · pF/μW small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has 10 V · pF/μs · μW large-signal FOM and 92 MHz · pF/μW small-signal FOM with 0.5-V supply voltage.Publication Open Access Analog lock-in amplifier design using subsampling for accuracy enhancement in GMI sensor applications(MDPI, 2023) Algueta-Miguel, Jose M.; Beato López, Juan Jesús; López Martín, Antonio; Ciencias; Zientziak; Institute of Smart Cities - ISC; Institute for Advanced Materials and Mathematics - INAMAT2; Universidad Pública de Navarra / Nafarroako Unibertsitate Publikoa, PJUPNA2005A frequency downscaling technique for enhancing the accuracy of analog lock-in amplifier (LIA) architectures in giant magneto-impedance (GMI) sensor applications is presented in this paper. As a proof of concept, the proposed method is applied to two different LIA topologies using, respectively, analog and switching-based multiplication for phase-sensitive detection. Specifically, the operation frequency of both the input and the reference signals of the phase-sensitive detector (PSD) block of the LIA is reduced through a subsampling process using sample-and-hold (SH) circuits. A frequency downscaling from 200 kHz, which is the optimal operating frequency of the employed GMI sensor, to 1 kHz has been performed. In this way, the proposed technique exploits the inherent advantages of analog signal multiplication at low frequencies, while the principle of operation of the PSD remains unaltered. The circuits were assembled using discrete components, and the frequency downscaling proposal was experimentally validated by comparing the measurement accuracy with the equivalent conventional circuits. The experimental results revealed that the error in the signal magnitude measurements was reduced by a factor of 8 in the case of the analog multipliers and by a factor of 21 when a PSD based on switched multipliers was used. The error in-phase detection using a two-phase LIA was also reduced by more than 25%.