López Martín, Antonio
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López Martín
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Antonio
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Ingeniería Eléctrica, Electrónica y de Comunicación
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ISC. Institute of Smart Cities
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22 results
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Now showing 1 - 10 of 22
Publication Open Access Enhanced single-stage folded cascode OTA suitable for large capacitive loads(IEEE, 2018) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCAn enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gainbandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5-µm CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.Publication Open Access CMOS first-order all-pass filter with 2-Hz pole frequency(IEEE, 2019) Paul, Anindita; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenA CMOS fully integrated all-pass filter with an extremely low pole frequency of 2 Hz is introduced in this paper. It has 0.08-dB passband ripple and 0.029-mm2 Si area. It has 0.38-mW power consumption in strong inversion with ±0.6-V power supplies. In subthreshold, it has 0.64-uW quiescent power and operates with ±200-mV dc supplies. Miller multiplication is used to obtain a large equivalent capacitor without excessive Si area. By varying the gain of the Miller amplifier, the pole frequency can be varied from 2 to 48 Hz. Experimental and simulation results of a test chip prototype in 130-nm CMOS technology validate the proposed circuit.Publication Open Access Gain-boosted super class AB OTAs based on nested local feedback(IEEE, 2021) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica y ElectrónicaA new approach to design super class AB operational transcon-ductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOML) of 236 V-1. To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.Publication Open Access Class AB amplifier with enhanced slew rate and GBW(John Wiley & Sons, 2019) Garde Luque, María Pilar; López Martín, Antonio; Algueta-Miguel, Jose M.; Ramírez-Angulo, Jaime; González Carvajal, Ramón; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenThe design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the Quasi-Floating Gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5 um CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.Publication Open Access 1-V 15-μW 130-nm CMOS super class AB OTA(IEEE, 2020) López Martín, Antonio; Algueta-Miguel, Jose M.; Garde Luque, María Pilar; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCA super class AB recycling folded cascode amplifier in 130 nm CMOS is presented. It combines for the first time adaptive biasing of the differential input pair, nonlinear current mirrors with current starving and dynamic biasing of the cascode transistors in the output branch. Measurements using a ±0.5V supply show slew rate and gain bandwidth product improvement factors of 26 and 112 versus the conventional topology for the same bias currents, yielding the highest combined FoM to date.Publication Open Access A highly efficient composite class-AB–AB Miller op-amp with high gain and stable from 15 pF up to very large capacitive loads(IEEE, 2018) Pourashraf, Shirin; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenIn this paper, a highly power-efficient class-AB–AB Miller op-amp is discussed. The structure uses gm enhancement based on local common-mode feedback to provide class-AB operation with enhanced effective gm , open-loop gain, unity-gain frequency, and slew rate ( SR ) without significant increase in quiescent power consumption. Utilization of a nonlinear load leads to large symmetric positive and negative SRs . Stability over an extremely wide range of capacitive loads is achieved through a combination of Miller and phase-lead compensations. The unity-gain frequency does not show sensitivity to capacitive load values. A test chip prototype fabricated in 0.18- μm CMOS technology shows 90.8-dB open-loop gain, 12.5-MHz bandwidth for a 25-pF load capacitance, and a factor 60 SR enhancement with maximum output current close to 1-mA and 43- μA total static current.Publication Open Access Folded Cascode OTA with 5540 MHzpF/mA FoM(IEEE, 2018) Garde Luque, María Pilar; López Martín, Antonio; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenA micropower single-stage folded cascode amplifier able to drive a wide range of capacitive loads is presented. It features class AB operation and includes power-efficient adaptive biasing techniques, which provide enhanced dynamic output current boosting and gain-bandwidth product (GBW). Phase lead compensation is used to improve phase margin and settling performance for low capacitive loads. Measurement results for a 0.5 μm CMOS process show a FoM of 5540 MHz pF/mA, the highest one reported to date for a folded cascode amplifier to the authors' knowledge.Publication Open Access Wide-swing class AB regulated cascode current mirror(IEEE, 2020) Garde Luque, María Pilar; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISCA micropower regulated cascode CMOS current mirror is presented, combining floating gate and quasi floating gate MOS transistors to achieve both wide swing and class AB operation, respectively. Measurement results for a 0.5 μm CMOS test chip prototype are included, showing that the current mirror can provide a THD at 100 kHz of -44 dB for a supply voltage of ±0.75 V and input current amplitudes 20 times larger than the bias current.Publication Open Access Super-gain-boosted AB-AB fully differential Miller op-amp with 156dB open-loop gain and 174MV/V MHZ pF/uW figure of merit in 130nm CMOS technology(IEEE, 2021) Paul, Anindita; Ramírez-Angulo, Jaime; Díaz Sánchez, Alejandro; López Martín, Antonio; González Carvajal, Ramón; Li, Frank X.; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de ComunicaciónA fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/uW and large-signal figure of merit FOMLS of 3(V/us) pF/uW.Publication Open Access Super-gain-boosted miller op-amp based on nested regulated cascode techniques with FoMAOLDC =24,614kV/V.MHz.pF/µWatt(IEEE, 2020) Paul, Anindita; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Díaz Sánchez, Alejandro; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio IngeniaritzarenA simple technique to greatly enhance the DC open-loop gain of a Miller op-amp is introduced here. It is based on the utilization of nested regulated cascode amplifiers. It uses conventional Miller compensation and does not increase the supply voltage. The proposed scheme has a DC open-loop gain Figure of Merit FoMAOLDC=24,614kV/V.pF.MHz/µWatt. It is especially appropriate for utilization in modern deep sub-micrometer CMOS technologies with low intrinsic gain.
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