Two-stage OTA with all subthreshold MOSFETs and optimum GBW to DC-current ratio
| dc.contributor.author | Beloso Legarra, Javier | |
| dc.contributor.author | Grasso, A. | |
| dc.contributor.author | López Martín, Antonio | |
| dc.contributor.author | Palumbo, Gaetano | |
| dc.contributor.author | Pennisi, Salvatore | |
| dc.contributor.department | Institute of Smart Cities - ISC | en |
| dc.date.accessioned | 2022-09-08T08:43:02Z | |
| dc.date.available | 2023-03-03T00:00:14Z | |
| dc.date.issued | 2022 | |
| dc.date.updated | 2022-09-08T08:37:10Z | |
| dc.description.abstract | An approach for the design of two-stage classAB OTAs with sub-1µA current consumption is proposed and demonstrated. The approach employs MOS transistors operating in subthreshold and allows maximum gain-bandwidth product (GBW) to be achieved for a given DC current budget, by setting optimum distribution of DC currents in the two amplifier stages. Following this strategy, a class AB OTA was designed in a standard 0.5-µm CMOS technology supplied from 1.6-V and experimentally tested. Measured GBW was 307 kHz with 980-nA DC current consumption while driving an output capacitance of 40 pF with an average slew rate of 96 V/ms | en |
| dc.description.sponsorship | This work was supported in part by Agenzia Estatal de Investigación (AEI), Ministerio de Ciencia e Innovación, Spanish Government under Grant PID2019-107258RB-C32 | en |
| dc.embargo.lift | 2023-03-03 | |
| dc.embargo.terms | 2023-03-03 | |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.citation | Beloso-Legarra, J.; Grasso A.; Lopez-Martin, A.; Palumbo, G.; Pennisi, S.. (2022). Two-stage OTA with all subthreshold MOSFETs and optimum GBW to DC-current ratio. IEEE Transactions on circuits and systems II: Express briefs. | en |
| dc.identifier.doi | 10.1109/TCSII.2022.3156401 | |
| dc.identifier.issn | 1549-7747 | |
| dc.identifier.uri | https://academica-e.unavarra.es/handle/2454/43976 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en |
| dc.relation.ispartof | IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 69, no. 7, July 2022 | en |
| dc.relation.projectID | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107258RB-C32/ES/ | |
| dc.relation.publisherversion | https://doi.org/10.1109/TCSII.2022.3156401 | |
| dc.rights | © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work. | en |
| dc.rights.accessRights | info:eu-repo/semantics/openAccess | |
| dc.subject | Circuits and systems | en |
| dc.subject | CMOS | en |
| dc.subject | Low power design | en |
| dc.subject | Miller compensation | en |
| dc.subject | MOSFET | en |
| dc.subject | Power demand | en |
| dc.subject | Resistors | en |
| dc.subject | Standards | en |
| dc.subject | Subthreshold operation | en |
| dc.subject | Transconductance | en |
| dc.subject | Transistors | en |
| dc.subject | Two-stage amplifier | en |
| dc.title | Two-stage OTA with all subthreshold MOSFETs and optimum GBW to DC-current ratio | en |
| dc.type | info:eu-repo/semantics/article | |
| dc.type.version | info:eu-repo/semantics/acceptedVersion | |
| dspace.entity.type | Publication | |
| relation.isAuthorOfPublication | 68898efd-37a6-48c7-8e2c-0fd2ab00a2a5 | |
| relation.isAuthorOfPublication | d3dc0470-6429-43e7-80f2-15fae67f4204 | |
| relation.isAuthorOfPublication.latestForDiscovery | 68898efd-37a6-48c7-8e2c-0fd2ab00a2a5 |