Analysis and design of PFDs in Cadence

This study aims to show the characteristics and behavior of some phase frequency detectors designs in order to improve some important aspects as the delay time and the power consumption in the classical model. For this, Cadence environment will be used, taking advantage of its potential and versatility in the design, implementation and analysis of IC circuits. Cadence is the main IC software design and the most used by circuit designers. The aim of this thesis is to deepen the concept of the PFD, to know its basic performance and recognize their limitations in order to resolve them in future designs as the ones which are shown here. So, watching the properties of these new designs will be able to choose one or the other depending on the benefits and drawbacks of each.