Power efficient simple technique to convert a reset-and-hold into a true-sample-and-hold using an auxiliary output stage
| dc.contributor.author | Rico-Aniles, Héctor Daniel | |
| dc.contributor.author | Ramírez-Angulo, Jaime | |
| dc.contributor.author | López Martín, Antonio | |
| dc.contributor.author | González Carvajal, Ramón | |
| dc.contributor.author | Rocha-Pérez, José Miguel | |
| dc.contributor.author | Garde Luque, María Pilar | |
| dc.contributor.department | Ingeniería Eléctrica, Electrónica y de Comunicación | es_ES |
| dc.contributor.department | Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren | eu |
| dc.date.accessioned | 2020-08-06T08:35:30Z | |
| dc.date.available | 2020-08-06T08:35:30Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%. The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the proposed technique. | en |
| dc.description.sponsorship | This work was supported by a Grant TEC2016-80396-C2 (AEI/FEDER). The work of Héctor Daniel Rico-Aniles was supported by the Mexican Consejo Nacional de Ciencia y Tecnología (CONACYT) through an academic scholarship under Grant 408946. | en |
| dc.format.extent | 9 p. | |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.citation | H. D. Rico-Aniles, J. Ramírez-Angulo, A. J. Lopez-Martin, R. G. Carvajal, J. M. Rocha-Pérez and M. Pilar Garde, 'Power Efficient Simple Technique to Convert a Reset-and-Hold Into a True-Sample-and-Hold Using an Auxiliary Output Stage,' in IEEE Access, vol. 8, pp. 66508-66516, 2020, doi: 10.1109/ACCESS.2020.2985256. | en |
| dc.identifier.doi | 10.1109/ACCESS.2020.2985256 | |
| dc.identifier.issn | 2169-3536 | |
| dc.identifier.uri | https://academica-e.unavarra.es/handle/2454/37741 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en |
| dc.relation.ispartof | IEEE Access, 2020, 8, 66508-66516 | en |
| dc.relation.projectID | info:eu-repo/grantAgreement/ES/1PE/TEC2016-80396/ | |
| dc.relation.publisherversion | https://doi.org/10.1109/ACCESS.2020.2985256 | |
| dc.rights | This work is licensed under a Creative Commons Attribution 4.0 License. | en |
| dc.rights.accessRights | info:eu-repo/semantics/openAccess | |
| dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ | |
| dc.subject | Amplifiers | en |
| dc.subject | Mixed-signal circuits | en |
| dc.subject | Offset compensation | en |
| dc.subject | Track-and-hold | en |
| dc.subject | Sample-andhold (S/H) | en |
| dc.subject | Switched capacitor | en |
| dc.title | Power efficient simple technique to convert a reset-and-hold into a true-sample-and-hold using an auxiliary output stage | en |
| dc.type | info:eu-repo/semantics/article | |
| dc.type.version | info:eu-repo/semantics/publishedVersion | |
| dspace.entity.type | Publication | |
| relation.isAuthorOfPublication | d3dc0470-6429-43e7-80f2-15fae67f4204 | |
| relation.isAuthorOfPublication | f2121138-6df7-4bfd-883f-fb35f21d9b9d | |
| relation.isAuthorOfPublication.latestForDiscovery | d3dc0470-6429-43e7-80f2-15fae67f4204 |