A novel PLL architecture
| dc.contributor.author | Osa, Juan I. | |
| dc.contributor.author | Carlosena García, Alfonso | |
| dc.contributor.author | López Martín, Antonio | |
| dc.contributor.department | Ingeniería Eléctrica y Electrónica | es_ES |
| dc.contributor.department | Ingeniaritza Elektrikoa eta Elektronikoa | eu |
| dc.date.accessioned | 2017-02-10T09:41:44Z | |
| dc.date.available | 2017-02-10T09:41:44Z | |
| dc.date.issued | 2000 | |
| dc.description | Trabajo presentado al XV Simposium Nacional de la Unión Científica de Radio (URSI '00), Zaragoza, 2000 | es_ES |
| dc.description.abstract | A novel phase-locked loop scheme is proposed in this paper, whose main distinguishing features are infinite hold-in range, pull-out range fractionally constant and also a ripple fractionally constant. To this end, it incorporates a variable gain amplifer and a frequency tunable loop filter. The driving application is the on-chip automatic tuning of slave filters, although the PLL architecture can be employed in many other applications. | en |
| dc.description.sponsorship | This work has been suported by the CICYT under grant TIC 97-418-C02-01. | en |
| dc.format.extent | 2 p. | |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.uri | https://academica-e.unavarra.es/handle/2454/23549 | |
| dc.language.iso | eng | en |
| dc.rights.accessRights | info:eu-repo/semantics/openAccess | |
| dc.subject | Phase-locked loop architecture | en |
| dc.title | A novel PLL architecture | en |
| dc.type | info:eu-repo/semantics/conferenceObject | |
| dc.type.version | info:eu-repo/semantics/publishedVersion | |
| dspace.entity.type | Publication | |
| relation.isAuthorOfPublication | 5496a010-31bd-4211-ab51-c8f575a8545e | |
| relation.isAuthorOfPublication | d3dc0470-6429-43e7-80f2-15fae67f4204 | |
| relation.isAuthorOfPublication.latestForDiscovery | 5496a010-31bd-4211-ab51-c8f575a8545e |