Listar por autor UPNA "Ugarte Gil, Mikel"
Mostrando ítems 1-2 de 2
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High-order PLL design with constant phase margin
In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed ... -
Performance comparison and design guidelines for Type II and Type III PLLs
The advantages provided by Type III PLLs are poorly known, since these devices are very often considered unstable and difficult, or even impossible, to design. In this paper, a performance comparison between Type II and ...