Publication: High-order PLL design with constant phase margin
Consultable a partir de
Date
2010
Director
Publisher
IEEE
Acceso abierto / Sarbide irekia
Contribución a congreso / Biltzarrerako ekarpena
Versión aceptada / Onetsi den bertsioa
Project identifier
Abstract
In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed by the authors, and is supported by extensive simulations and experimental results, giving up to a type-III fifth-order PLL with a commercial circuit.
Keywords
High-order PLL design, Constant phase margin
Department
Ingeniería Eléctrica y Electrónica / Ingeniaritza Elektrikoa eta Elektronikoa
Faculty/School
Degree
Doctorate program
Editor version
Funding entities
This work has been supported in part
by the Spanish Dirección General de Investigación and
FEDER under grants TEC2007-67460-C03/01 and DPI2007-
66615-C02-01.
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