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Ugarte Gil, Mikel

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Ugarte Gil

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Mikel

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2010 - 20152
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    PublicationOpen Access
    High-order PLL design with constant phase margin
    (IEEE, 2010) Ugarte Gil, Mikel; Carlosena García, Alfonso; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed by the authors, and is supported by extensive simulations and experimental results, giving up to a type-III fifth-order PLL with a commercial circuit.
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    PublicationOpen Access
    Performance comparison and design guidelines for Type II and Type III PLLs
    (Birkhauser, 2015) Ugarte Gil, Mikel; Carlosena García, Alfonso; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    The advantages provided by Type III PLLs are poorly known, since these devices are very often considered unstable and difficult, or even impossible, to design. In this paper, a performance comparison between Type II and III PLLs is presented, based on an alternative model introduced by the authors. More precisely, the devices are exposed to chirp type and even more complex signals to demonstrate that Type III PLLs may offer better results in terms of phase margin and frequency response peaking when properly designed. As a result of our analysis, approximate closed form expressions will be proposed to evaluate Type III PLL performance and its relation to the parameters of the model.