Open Access
Low-voltage 0.81mW, 1-32 CMOS VGA with 5% bandwidth variations and -38dB DC rejection
(IEEE, 2020) López Martín, Antonio; Rico-Aniles, Héctor Daniel; Ramírez-Angulo, Jaime; Rocha-Pérez, José Miguel; González Carvajal, Ramón; Institute of Smart Cities - ISC
A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants. It operates with +/-0:45V supplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit FOMSS=5380 (MHz*pF/mW) and FOMLS=0:0085((V/ns)*pF/mA) for a nominal gain A=32.
Open Access
Energy-efficient amplifiers based on quasi-floating gate techniques
(MDPI, 2021) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Beloso Legarra, Javier; González Carvajal, Ramón; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.
Open Access
±0.3v bulk-driven fully differential buffer with high figures of merit
(MDPI, 2022) Gangineni, Manaswini; Ramírez-Angulo, Jaime; Vázquez-Leal, Héctor; Huerta-Chua, Jesús; López Martín, Antonio; González Carvajal, Ramón; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, high CMRR bulk-driven pseudo-differential cells. It operates in subthreshold, has infinite input impedance, low output impedance (1.4 kΩ), 86.77 dB DC open-loop gain, 172.91 kHz bandwidth and 0.684 µWstatic power dissipation with a 50-pF load capacitance. The buffer has power efficient class AB operation, a small signal figure of merit FOMss = 12.69 MHzpFµW-1, a large signal figure of merit FOMls = 34.89 (V/µs) pFµW-1, CMRR = 102 dB, PSRR+ = 109 dB, PSRR- = 100 dB, 1.1 µV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.
Open Access
Super-gain-boosted miller op-amp based on nested regulated cascode techniques with FoMAOLDC =24,614kV/V.MHz.pF/µWatt
(IEEE, 2020) Paul, Anindita; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Díaz Sánchez, Alejandro; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
A simple technique to greatly enhance the DC open-loop gain of a Miller op-amp is introduced here. It is based on the utilization of nested regulated cascode amplifiers. It uses conventional Miller compensation and does not increase the supply voltage. The proposed scheme has a DC open-loop gain Figure of Merit FoMAOLDC=24,614kV/V.pF.MHz/µWatt. It is especially appropriate for utilization in modern deep sub-micrometer CMOS technologies with low intrinsic gain.
Open Access
360 nW gate-driven ultra-low voltage CMOS linear transconductor with 1 MHz bandwidth and wide input range
(IEEE, 2020) Rico-Aniles, Héctor Daniel; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
A low voltage linear transconductor is introduced. The circuit is a pseudo differential architecture that operates with ±0.2V supplies and uses 900nA total biasing current. It employs a floating battery technique to achieve low voltage operation. The transconductor has a 1MHz bandwidth. It exhibits a SNR = 72dB, SFDR = 42dB and THD = 0.83% for a 100mVpp 10kHz sinusoidal input signal. Moreover, stability is not affected by the capacitance of the signal source. The circuit has been validated with a prototype chip fabricated in a 130nm CMOS technology.
Open Access
Super-gain-boosted AB-AB fully differential Miller op-amp with 156dB open-loop gain and 174MV/V MHZ pF/uW figure of merit in 130nm CMOS technology
(IEEE, 2021) Paul, Anindita; Ramírez-Angulo, Jaime; Díaz Sánchez, Alejandro; López Martín, Antonio; González Carvajal, Ramón; Li, Frank X.; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/uW and large-signal figure of merit FOMLS of 3(V/us) pF/uW.
Open Access
Power efficient simple technique to convert a reset-and-hold into a true-sample-and-hold using an auxiliary output stage
(IEEE, 2020) Rico-Aniles, Héctor Daniel; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Rocha-Pérez, José Miguel; Garde Luque, María Pilar; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%. The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the proposed technique.
Open Access
An enhanced gain-bandwidth class-AB miller op-amp with 23,800 MHz pF/mW FOM, 11-16 current efficiency and wide range of resistive and capacitive loads driving capability
(IEEE, 2021) Paul, Anindita; Ramírez-Angulo, Jaime; Díaz Sánchez, Alejandro; López Martín, Antonio; González Carvajal, Ramón; Li, Frank X.; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica y Electrónica
A compact power-efficient class-AB Miller op-amp is introduced. It uses a simple auxiliary circuit that enhances the op-amp's gain-bandwidth product and helps to drive a wide range of capacitive and resistive loads with high static and dynamic current efficiency. Simple Miller compensation is used to obtain stability over a wide range of loading conditions. The op-amp's simulation and experimental results in strong inversion with 15uA bias current and in sub-threshold with 250nA bias current are shown. Its performance is measured in terms of dynamic and static current efficiency figures of merit FOMCEDyn and FOMCEStat: and using the conventional small-signal figure of merit FOMSS: Experimental results of op-amps fabricated in a 130nm CMOS technology are shown that validate the proposed approach.