Person:
López Martín, Antonio

person.page.identifierURI

https://academica-e.unavarra.es/handle/2454/49446

Last Name

López Martín

First Name

Antonio

person.page.departamento

Ingeniería Eléctrica, Electrónica y de Comunicación

person.page.instituteName

ISC. Institute of Smart Cities

ORCID

0000-0001-7629-0305

person.page.upna

2254

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Now showing 1 - 10 of 22

Open Access
On the optimal current followers for wide-swing current-efficient amplifiers
(IEEE, 2018) López Martín, Antonio; Garde Luque, María Pilar; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
The design of various current followers for the implementation of OTAs with high slew rate and current efficiency is addressed. Two basic current follower topologies are compared, and modifications of both followers to improve these parameters are presented. As an application example, an enhanced recycling folded cascode OTA is proposed. Measurement results of the OTA fabricated in a 0.5 μm CMOS process show a 260% and 180% improvement in SR and GBW, respectively, for the same power consumption.
Open Access
Low-voltage 0.81mW, 1-32 CMOS VGA with 5% bandwidth variations and -38dB DC rejection
(IEEE, 2020) López Martín, Antonio; Rico-Aniles, Héctor Daniel; Ramírez-Angulo, Jaime; Rocha-Pérez, José Miguel; González Carvajal, Ramón; Institute of Smart Cities - ISC
A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants. It operates with +/-0:45V supplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit FOMSS=5380 (MHz*pF/mW) and FOMLS=0:0085((V/ns)*pF/mA) for a nominal gain A=32.
Open Access
Pseudo-three-stage Miller op-amp with enhanced small-signal and large-signal performance
(IEEE, 2019) Paul, Anindita; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Rocha-Pérez, José Miguel; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
A simple technique to implement highly power efficient class AB-AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp's effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has 9 V·pF/μs·μW large-signal figure of merit (FOM) and 17 MHz · pF/μW small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has 10 V · pF/μs · μW large-signal FOM and 92 MHz · pF/μW small-signal FOM with 0.5-V supply voltage.
Open Access
Super class AB RFC OTA using non-linear current mirrors
(Institution of Engineering and Technology, 2018) Garde Luque, María Pilar; López Martín, Antonio; Carvajal, Ramón G.; Galán, J.A.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISC
An alternative approach to the design of super class AB recycling folded cascode operational transconductance amplifiers is proposed. Instead of using local common-mode feedback for boosting dynamic currents, simple current mirrors with input transistors entering triode region for large currents are employed. Measurement results from a 0.5 μm CMOS test chip validate the proposal.
Open Access
Wide-swing class AB regulated cascode current mirror
(IEEE, 2020) Garde Luque, María Pilar; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISC
A micropower regulated cascode CMOS current mirror is presented, combining floating gate and quasi floating gate MOS transistors to achieve both wide swing and class AB operation, respectively. Measurement results for a 0.5 μm CMOS test chip prototype are included, showing that the current mirror can provide a THD at 100 kHz of -44 dB for a supply voltage of ±0.75 V and input current amplitudes 20 times larger than the bias current.
Open Access
Enhanced single-stage folded cascode OTA suitable for large capacitive loads
(IEEE, 2018) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISC
An enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gainbandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5-µm CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.
Open Access
Super class AB RFC OTA with adaptive local common-mode feedback
(Institution of Engineering and Technology, 2018) Garde Luque, María Pilar; López Martín, Antonio; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
A super class AB recycling folded cascode operational transconductance amplifier is presented. It employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads. Measurement results from a test chip prototype fabricated in a 0.5 μm CMOS process validate the proposal.
Open Access
CMOS first-order all-pass filter with 2-Hz pole frequency
(IEEE, 2019) Paul, Anindita; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
A CMOS fully integrated all-pass filter with an extremely low pole frequency of 2 Hz is introduced in this paper. It has 0.08-dB passband ripple and 0.029-mm2 Si area. It has 0.38-mW power consumption in strong inversion with ±0.6-V power supplies. In subthreshold, it has 0.64-uW quiescent power and operates with ±200-mV dc supplies. Miller multiplication is used to obtain a large equivalent capacitor without excessive Si area. By varying the gain of the Miller amplifier, the pole frequency can be varied from 2 to 48 Hz. Experimental and simulation results of a test chip prototype in 130-nm CMOS technology validate the proposed circuit.
Open Access
Super-gain-boosted AB-AB fully differential Miller op-amp with 156dB open-loop gain and 174MV/V MHZ pF/uW figure of merit in 130nm CMOS technology
(IEEE, 2021) Paul, Anindita; Ramírez-Angulo, Jaime; Díaz Sánchez, Alejandro; López Martín, Antonio; González Carvajal, Ramón; Li, Frank X.; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/uW and large-signal figure of merit FOMLS of 3(V/us) pF/uW.
Open Access
±0.25 V Class-AB CMOS capacitance multiplier and precision rectifiers
(IEEE, 2019) Pourashraf, Shirin; Ramírez-Angulo, Jaime; Hinojo Montero, José María; González Carvajal, Ramón; López Martín, Antonio; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
Reduction of minimum supply requirements is a crucial aspect to decrease the power consumption in VLSI systems. A high performance capacitance multiplier able to operate with supplies as low as ±0.25 V is presented. It is based on adaptively biased class-AB current mirrors which provide high current efficiency. Measurement results of a factor 11 capacitance multiplier fabricated in 180 nm CMOS technology verify theoretical claims. Moreover, low-voltage precision rectifiers based on the same class-AB current mirrors are designed and fabricated in the same CMOS process. They generate output currents over 100 times larger than the quiescent current. Both proposed circuits have 300 nW static power dissipation when operating with ±0.25 V supplies.