López Martín, Antonio

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López Martín

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Antonio

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Ingeniería Eléctrica, Electrónica y de Comunicación

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ISC. Institute of Smart Cities

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Now showing 1 - 10 of 45
  • PublicationOpen Access
    Energy harvesting approaches in IoT scenarios with very low ambient energy
    (European Association for the Development of Renewable Energy, Environment and Power Quality (EA4EPQ), 2019) López Martín, Antonio; Algueta-Miguel, Jose M.; Matías Maestro, Ignacio; Institute of Smart Cities - ISC
    The feasibility of multi-source energy harvesting in Internet of Things (IoT) scenarios with low and intermittent ambient energy is addressed. As a relevant case study, application to a smart cargo container system is analysed. The most relevant features of the main energy sources available in this target application are identified, and various transducers adapted to such sources are evaluated. Measurement results indicate that combined piezoelectric and thermoelectric generation inside cargo containers can significantly extend the battery lifetime of IoT end nodes embedded in such containers.
  • PublicationOpen Access
    Pseudo-three-stage Miller op-amp with enhanced small-signal and large-signal performance
    (IEEE, 2019) Paul, Anindita; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Rocha-Pérez, José Miguel; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
    A simple technique to implement highly power efficient class AB-AB Miller op-amps is presented in this paper. It uses a composite input stage with resistive local common mode feedback that provides class AB operation to the input stage and essentially enhances the op-amp's effective transconductance gain, the dc open-loop gain, the gain-bandwidth product, and slew rate with just moderate increase in power dissipation. The experimental results of op-amps in strong inversion and subthreshold fabricated in a 130-nm standard CMOS technology validate the proposed approach. The op-amp has 9 V·pF/μs·μW large-signal figure of merit (FOM) and 17 MHz · pF/μW small-signal FOM with 1.2-V supply voltage. In subthreshold, the op-amp has 10 V · pF/μs · μW large-signal FOM and 92 MHz · pF/μW small-signal FOM with 0.5-V supply voltage.
  • PublicationOpen Access
    Design of MOS-translinear multiplier/dividers in analog VLSI
    (Hindawi Publishing Corporation, 2000) López Martín, Antonio; Carlosena García, Alfonso; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/ divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-1am CMOS process, are provided in order to verify the correctness of the proposed approach.
  • PublicationOpen Access
    Analog lock-in amplifier design using subsampling for accuracy enhancement in GMI sensor applications
    (MDPI, 2023) Algueta-Miguel, Jose M.; Beato López, Juan Jesús; López Martín, Antonio; Ciencias; Zientziak; Institute of Smart Cities - ISC; Institute for Advanced Materials and Mathematics - INAMAT2; Universidad Pública de Navarra / Nafarroako Unibertsitate Publikoa, PJUPNA2005
    A frequency downscaling technique for enhancing the accuracy of analog lock-in amplifier (LIA) architectures in giant magneto-impedance (GMI) sensor applications is presented in this paper. As a proof of concept, the proposed method is applied to two different LIA topologies using, respectively, analog and switching-based multiplication for phase-sensitive detection. Specifically, the operation frequency of both the input and the reference signals of the phase-sensitive detector (PSD) block of the LIA is reduced through a subsampling process using sample-and-hold (SH) circuits. A frequency downscaling from 200 kHz, which is the optimal operating frequency of the employed GMI sensor, to 1 kHz has been performed. In this way, the proposed technique exploits the inherent advantages of analog signal multiplication at low frequencies, while the principle of operation of the PSD remains unaltered. The circuits were assembled using discrete components, and the frequency downscaling proposal was experimentally validated by comparing the measurement accuracy with the equivalent conventional circuits. The experimental results revealed that the error in the signal magnitude measurements was reduced by a factor of 8 in the case of the analog multipliers and by a factor of 21 when a PSD based on switched multipliers was used. The error in-phase detection using a two-phase LIA was also reduced by more than 25%.
  • PublicationOpen Access
    Sensing in coin discriminators
    (IEEE, 2007) Carlosena García, Alfonso; López Martín, Antonio; Arizti, Fernando; Martínez de Guereñu, Ane; Pina Insausti, José L.; García Sayés, Miguel; Ingeniería Eléctrica y Electrónica; Ingeniaritza Elektrikoa eta Elektronikoa
    This paper describes the technologies used in coin discriminator devices, stressing the improvements and novel mechanisms introduced by the authors in the past few years as a result of the cooperation with one leading company in the vending sector. Emphasis is put on how low-cost sensors are used to characterize coins (or tokens) and discriminate them from their counterfeits.
  • PublicationOpen Access
    Micropower class AB low-pass analog filter based on the super-source follower
    (IEEE, 2022) Martincorena Arraiza, Maite; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Carlosena García, Alfonso; Institute of Smart Cities - ISC
    An improved class AB version of the super source follower is used to implement a compact and power-efficient second order analog low-pass filter. The proposed circuit achieves a 41% power reduction as well as an improvement in linearity and pass band gain with respect to its class A counterpart. Measurement results of a test chip prototype fabricated in a 180 nm CMOS technology show a power consumption ranging from 50.3 μW to 85.27 μW for cutoff frequencies from 600 kHz to 890 kHz, with a supply voltage of ±0.75 V. A third order intermodulation distortion of −35.34 dB (for an input signal of 0.4 mV pp and 350 kHz) and a THD of −69.7 dB (for an input signal of 0.4 mV pp and 100 kHz) are measured, which results in an improvement with respect to the conventional class A version of 13.98 dB and 43.6 dB, respectively. The silicon area is 0.0592 mm 2 (using external capacitors).
  • PublicationOpen Access
    AC coupled amplifier with a resistance multiplier technique for ultra-low frequency operation
    (Elsevier, 2022) Martincorena Arraiza, Maite; Cruz Blas, Carlos Aristóteles de la; Carlosena García, Alfonso; López Martín, Antonio; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación; Universidad Pública de Navarra / Nafarroako Unibertsitate Publikoa
    This paper proposes a novel, tunable AC coupled capacitive feedback amplifier, exhibiting an ultra-low high pass corner frequency. This is accomplished by actively boosting the output resistive value of a MOS transistor in weak inversion. The circuit is based on a more general architecture, recently proposed by the authors, and is analyzed in terms of its capability to achieve ultra-low frequency operation, its DC performance, and noise. The proposed technique is demonstrated via measurement results from a fabricated test chip prototype using a standard 0.18 µm CMOS technology. The proposed amplifier provides a tunable high pass corner frequency from 20 mHz to 475 mHz, consuming 4.71 μW and a total area of 0.069 mm2.
  • PublicationOpen Access
    Super class AB RFC OTA with adaptive local common-mode feedback
    (Institution of Engineering and Technology, 2018) Garde Luque, María Pilar; López Martín, Antonio; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
    A super class AB recycling folded cascode operational transconductance amplifier is presented. It employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads. Measurement results from a test chip prototype fabricated in a 0.5 μm CMOS process validate the proposal.
  • PublicationOpen Access
    Buscando claves para promover la participación de la mujer en estudios de Ingeniería de Telecomunicación
    (Educación Editora, 2014) Alejos, Ana V.; Milagros, María Pilar; Falcone Lanas, Francisco; López Martín, Antonio; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoa eta Telekomunikazio Ingeniaritza
    En la presente contribución se discute la necesidad de analizar el problema de la escasa presencia de la mujer en los estudios de Ingeniería de Telecomunicación. Se describe una encuesta en curso para indagar los factores de la segregación de género en esta carrera. Asimismo, se propone trasladar al aula medidas que capten una mayor presencia femenina.
  • PublicationOpen Access
    Enhanced single-stage folded cascode OTA suitable for large capacitive loads
    (IEEE, 2018) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISC
    An enhanced single-stage folded cascode operational transconductance amplifier able to drive large capacitive loads is presented. Circuits that adaptively bias the input differential pair and the current folding stage are employed, which provide class AB operation with dynamic current boosting and increased gainbandwidth (GBW) product. Measurement results of a test chip prototype fabricated in a 0.5-µm CMOS process show an increase in slew rate and GBW by a factor of 30 and 15, respectively, versus the class A version using the same supply voltage and bias currents. Overhead in other performance metrics is small.