Open Access
Energy-efficient amplifiers based on quasi-floating gate techniques
(MDPI, 2021) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Beloso Legarra, Javier; González Carvajal, Ramón; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.
Open Access
Low-voltage 0.81mW, 1-32 CMOS VGA with 5% bandwidth variations and -38dB DC rejection
(IEEE, 2020) López Martín, Antonio; Rico-Aniles, Héctor Daniel; Ramírez-Angulo, Jaime; Rocha-Pérez, José Miguel; González Carvajal, Ramón; Institute of Smart Cities - ISC
A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants. It operates with +/-0:45V supplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit FOMSS=5380 (MHz*pF/mW) and FOMLS=0:0085((V/ns)*pF/mA) for a nominal gain A=32.
Open Access
Distributed opportunistic wireless mapping system towards smart city service provision
(IEEE, 2021) Villadangos Alonso, Jesús; Falcone Lanas, Francisco; López Martín, Antonio; Astrain Escola, José Javier; Sanchis Gúrpide, Pablo; Matías Maestro, Ignacio; Estatistika, Informatika eta Matematika; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Estadística, Informática y Matemáticas; Ingeniería Eléctrica, Electrónica y de Comunicación
The knowledge of wireless signal distribution within an urban scenario can provide useful information to users as well as to enhance connectivity and device operation or to perform municipal logistics based on crowd density and user mobility patterns. In this work, a distributed wireless mapping system, based on a combination of opportunistic nodes such as smartphones which map geolocated WiFi access point connection and received power levels, and a cloud-based information gathering architecture is described. The proposed system has been tested in the framework of the Smart City platform of the city of Pamplona, providing signal distribution heat maps, which can be used for multiple municipal services.
Open Access
A family of alternating current amplifiers for ultra-low frequency operation
(Wiley, 2021) Martincorena Arraiza, Maite; Carlosena García, Alfonso; Cruz Blas, Carlos Aristóteles de la; Beloso Legarra, Javier; López Martín, Antonio; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación; Universidad Pública de Navarra / Nafarroako Unibertsitate Publikoa
A family of capacitively coupled alternating current (AC) amplifiers featuring ultra-low (below 1 Hz) corner frequency is presented. This is achieved by using high-gain devices which actively boost feedback resistance and thus reduce corner frequency. This procedure is often termed, though with a different purpose, as 'bootstrapping'. The proposed architectures are very general and admit several possible practical implementations. To demonstrate their usefulness, the circuits are implemented with two operational amplifiers (OA), but other active devices such as operational transconductance amplifiers (OTAs) can be alternatively used. All circuits have been theoretically analyzed, extensively simulated and measured, exhibiting high-pass cutoff frequencies as low as 30 mHz.
Open Access
Wide-swing class AB regulated cascode current mirror
(IEEE, 2020) Garde Luque, María Pilar; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISC
A micropower regulated cascode CMOS current mirror is presented, combining floating gate and quasi floating gate MOS transistors to achieve both wide swing and class AB operation, respectively. Measurement results for a 0.5 μm CMOS test chip prototype are included, showing that the current mirror can provide a THD at 100 kHz of -44 dB for a supply voltage of ±0.75 V and input current amplitudes 20 times larger than the bias current.
Open Access
Gain-boosted super class AB OTAs based on nested local feedback
(IEEE, 2021) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica y Electrónica
A new approach to design super class AB operational transcon-ductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOML) of 236 V-1. To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.
Open Access
Super-gain-boosted AB-AB fully differential Miller op-amp with 156dB open-loop gain and 174MV/V MHZ pF/uW figure of merit in 130nm CMOS technology
(IEEE, 2021) Paul, Anindita; Ramírez-Angulo, Jaime; Díaz Sánchez, Alejandro; López Martín, Antonio; González Carvajal, Ramón; Li, Frank X.; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/uW and large-signal figure of merit FOMLS of 3(V/us) pF/uW.
Open Access
360 nW gate-driven ultra-low voltage CMOS linear transconductor with 1 MHz bandwidth and wide input range
(IEEE, 2020) Rico-Aniles, Héctor Daniel; Ramírez-Angulo, Jaime; López Martín, Antonio; González Carvajal, Ramón; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
A low voltage linear transconductor is introduced. The circuit is a pseudo differential architecture that operates with ±0.2V supplies and uses 900nA total biasing current. It employs a floating battery technique to achieve low voltage operation. The transconductor has a 1MHz bandwidth. It exhibits a SNR = 72dB, SFDR = 42dB and THD = 0.83% for a 100mVpp 10kHz sinusoidal input signal. Moreover, stability is not affected by the capacitance of the signal source. The circuit has been validated with a prototype chip fabricated in a 130nm CMOS technology.
Open Access
An enhanced gain-bandwidth class-AB miller op-amp with 23,800 MHz pF/mW FOM, 11-16 current efficiency and wide range of resistive and capacitive loads driving capability
(IEEE, 2021) Paul, Anindita; Ramírez-Angulo, Jaime; Díaz Sánchez, Alejandro; López Martín, Antonio; González Carvajal, Ramón; Li, Frank X.; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica y Electrónica
A compact power-efficient class-AB Miller op-amp is introduced. It uses a simple auxiliary circuit that enhances the op-amp's gain-bandwidth product and helps to drive a wide range of capacitive and resistive loads with high static and dynamic current efficiency. Simple Miller compensation is used to obtain stability over a wide range of loading conditions. The op-amp's simulation and experimental results in strong inversion with 15uA bias current and in sub-threshold with 250nA bias current are shown. Its performance is measured in terms of dynamic and static current efficiency figures of merit FOMCEDyn and FOMCEStat: and using the conventional small-signal figure of merit FOMSS: Experimental results of op-amps fabricated in a 130nm CMOS technology are shown that validate the proposed approach.
Open Access
1-V 15-μW 130-nm CMOS super class AB OTA
(IEEE, 2020) López Martín, Antonio; Algueta-Miguel, Jose M.; Garde Luque, María Pilar; Carvajal, Ramón G.; Ramírez-Angulo, Jaime; Institute of Smart Cities - ISC
A super class AB recycling folded cascode amplifier in 130 nm CMOS is presented. It combines for the first time adaptive biasing of the differential input pair, nonlinear current mirrors with current starving and dynamic biasing of the cascode transistors in the output branch. Measurements using a ±0.5V supply show slew rate and gain bandwidth product improvement factors of 26 and 112 versus the conventional topology for the same bias currents, yielding the highest combined FoM to date.