Publication: Design of MOS-translinear multiplier/dividers in analog VLSI
| dc.contributor.author | López Martín, Antonio | |
| dc.contributor.author | Carlosena García, Alfonso | |
| dc.contributor.department | Ingeniería Eléctrica y Electrónica | es_ES |
| dc.contributor.department | Ingeniaritza Elektrikoa eta Elektronikoa | eu |
| dc.date.accessioned | 2017-02-10T09:41:42Z | |
| dc.date.available | 2017-02-10T09:41:42Z | |
| dc.date.issued | 2000 | |
| dc.description.abstract | A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/ divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-1am CMOS process, are provided in order to verify the correctness of the proposed approach. | en |
| dc.description.sponsorship | Financial support from the CICYT under grant (TIC 97/0418-C02-01) and the Gobierno de Navarra are gratefully acknowledged. | en |
| dc.format.extent | 10 p. | |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.issn | 1065-514X (Print) | |
| dc.identifier.issn | 1563-5171 (Electronic) | |
| dc.identifier.uri | https://academica-e.unavarra.es/handle/2454/23543 | |
| dc.language.iso | eng | en |
| dc.publisher | Hindawi Publishing Corporation | en |
| dc.relation.ispartof | VLSI Design, 2000, Vol. 11, No. 4, pp. 321-329 | en |
| dc.rights | © 2000 OPA (Overseas Publishers Association) N.V. | en |
| dc.rights.accessRights | info:eu-repo/semantics/openAccess | |
| dc.subject | Analog multiplier/dividers | en |
| dc.subject | Multipliers | en |
| dc.subject | MOS-translinear | en |
| dc.subject | Voltage-translinear | en |
| dc.subject | CMOS analog circuits | en |
| dc.subject | Analog VLSI | en |
| dc.title | Design of MOS-translinear multiplier/dividers in analog VLSI | en |
| dc.type | info:eu-repo/semantics/article | |
| dc.type.version | Versión publicada / Argitaratu den bertsioa | es |
| dc.type.version | info:eu-repo/semantics/publishedVersion | en |
| dspace.entity.type | Publication | |
| relation.isAuthorOfPublication | d3dc0470-6429-43e7-80f2-15fae67f4204 | |
| relation.isAuthorOfPublication | 5496a010-31bd-4211-ab51-c8f575a8545e | |
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