Power-efficient CMOS amplifiers for battery-supplied systems

dc.contributor.advisorLópez Martín, Antonio
dc.contributor.advisorCruz Blas, Carlos Aristóteles de la
dc.contributor.authorBeloso Legarra, Javier
dc.contributor.departmentIngeniería Eléctrica, Electrónica y de Comunicaciónes_ES
dc.contributor.departmentIngeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzareneu
dc.date.accessioned2023-12-27T11:58:57Z
dc.date.available2023-12-27T11:58:57Z
dc.date.issued2023
dc.date.submitted2023-12-02
dc.description.abstractIn this Thesis, the design of power-efficient CMOS amplifiers that are suitable for battery-supplied systems with low-voltage and low-power constraints is developed. This type of circuit is essential in modern portable systems as it performs several signal processing functions, thus requiring high-performance characteristics. To this end, novel circuit-level design techniques and methodologies have been proposed with the aim of improving the performance of the amplifier while preserving simultaneously a reduced power dissipation. The following contributions are focused on single-stage and two-stage amplifier architectures. In the case of single-stage topologies, a unified approach that allows analyzing simultaneously in a common framework the most common single-stage amplifiers for a fixed current budget has been proposed, with the addition of the latest device and circuit level techniques. The design of power-efficient single-stage amplifiers is expanded by proposing several topologies based on non-linear current mirrors as class-AB current boosting technique operating in weak inversion. To illustrate their applicability in switched-capacitor circuits, a sample-and-hold has been designed. All these circuits have been implemented in a 180-nm process and validated experimentally. Finally, a novel design methodology for two-stage amplifiers operating in weak inversion region that optimizes the gain-bandwidth product for a given current budget by exploiting the frequency compensation is proposed. In order to validate the proposal, several experimental measurements of a prototype implemented in a 0.5-μm process have been performed.en
dc.description.doctorateProgramPrograma de Doctorado en Tecnologías de las Comunicaciones, Bioingeniería y de las Energías Renovables (RD 99/2011)es_ES
dc.description.doctorateProgramBioingeniaritzako eta Komunikazioen eta Energia Berriztagarrien Teknologietako Doktoretza Programa (ED 99/2011)eu
dc.format.extent105 p.
dc.format.mimetypeapplication/pdfen
dc.identifier.doi10.48035/Tesis/2454/46911
dc.identifier.urihttps://academica-e.unavarra.es/handle/2454/46911
dc.language.isoengen
dc.relation.publisherversionhttps://doi.org/10.48035/Tesis/2454/46911
dc.rights© Todos los derechos reservadosen
dc.rights.accessRightsinfo:eu-repo/semantics/openAccess
dc.subjectPower-efficient CMOS amplifiersen
dc.subjectSingle-stage amplifier architectureen
dc.subjectTwo-stage amplifier architectureen
dc.titlePower-efficient CMOS amplifiers for battery-supplied systemsen
dc.title.alternativeAmplificadores CMOS energéticamente eficientes para sistemas alimentados por bateríaes_ES
dc.typeinfo:eu-repo/semantics/doctoralThesis
dspace.entity.typePublication
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