High-order PLL design with constant phase margin
| dc.contributor.author | Ugarte Gil, Mikel | |
| dc.contributor.author | Carlosena García, Alfonso | |
| dc.contributor.department | Ingeniería Eléctrica y Electrónica | es_ES |
| dc.contributor.department | Ingeniaritza Elektrikoa eta Elektronikoa | eu |
| dc.date.accessioned | 2017-08-18T10:39:28Z | |
| dc.date.available | 2017-08-18T10:39:28Z | |
| dc.date.issued | 2010 | |
| dc.description.abstract | In this paper we describe a novel procedure to design high-type high-order Phase Locked Loops (PLLs) from lower order prototypes, preserving a prescribed Phase Margin (PM). The method builds on a model recently proposed by the authors, and is supported by extensive simulations and experimental results, giving up to a type-III fifth-order PLL with a commercial circuit. | en |
| dc.description.sponsorship | This work has been supported in part by the Spanish Dirección General de Investigación and FEDER under grants TEC2007-67460-C03/01 and DPI2007- 66615-C02-01. | en |
| dc.format.extent | 4 p. | |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.citation | M. Ugarte and A. Carlosena, "High-order PLL design with constant Phase Margin," 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, 2010, pp. 570-573. doi: 10.1109/MWSCAS.2010.5548890 | en |
| dc.identifier.doi | 10.1109/MWSCAS.2010.5548890 | |
| dc.identifier.isbn | 978-1-4244-7771-5 (Print) | |
| dc.identifier.isbn | 978-1-4244-7773-9 (Electronic) | |
| dc.identifier.issn | 1548-3746 (Print) | |
| dc.identifier.issn | 1558-3899 (Electronic) | |
| dc.identifier.uri | https://academica-e.unavarra.es/handle/2454/25230 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en |
| dc.relation.ispartof | 2010 53rd IEEE International Midwest Symposium on Circuits and Systems. Seattle (Estados Unidos), 2010, pp. 570-573. | en |
| dc.relation.publisherversion | https://doi.org/10.1109/MWSCAS.2010.5548890 | |
| dc.rights.accessRights | info:eu-repo/semantics/openAccess | |
| dc.subject | High-order PLL design | en |
| dc.subject | Constant phase margin | en |
| dc.title | High-order PLL design with constant phase margin | en |
| dc.type | info:eu-repo/semantics/conferenceObject | |
| dc.type.version | info:eu-repo/semantics/acceptedVersion | |
| dspace.entity.type | Publication | |
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| relation.isAuthorOfPublication.latestForDiscovery | 75eeeeb0-fc19-4492-941f-231f18cf8d37 |