Open Access
Energy-efficient amplifiers based on quasi-floating gate techniques
(MDPI, 2021) López Martín, Antonio; Garde Luque, María Pilar; Algueta-Miguel, Jose M.; Beloso Legarra, Javier; González Carvajal, Ramón; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación
Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.
Open Access
Single-stage class-AB non-linear current mirror OTA
(IEEE, 2022) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Institute of Smart Cities - ISC
The analysis, design and experimental characterization of a single-stage class-AB operational transconductance amplifier (OTA) with enhanced large- and small-signal performance is presented. The OTA is biased in weak inversion to save power and employs a non-linear current mirror as active load, leading a boosting current directly at the output branch. As a result, the amplifier's performance is improved without additional circuit elements and/or power consumption. A chip prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of 2.5 µW from a supply voltage of ±0.5 V and a silicon area of 0.0013 mm 2 . For a load of 160 pF, it exhibits an average slew rate of 0.94 V/µs and a gain-bandwidth product of 22.1 kHz.
Open Access
Diseño y test de convertidores analógico-digitales no lineales configurables usando Arduino Due
(2016) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; Escuela Técnica Superior de Ingenieros Industriales y de Telecomunicación; Telekomunikazio eta Industria Ingeniarien Goi Mailako Eskola Teknikoa
En el presente proyecto fin de grado se va a diseñar, implementar y testear una plataforma flexible y configurable de Conversores Analógico Digitales (CAD) no lineales. La plataforma consiste de dos partes; la primera está formada por un circuito integrado diseñado en la UPNA que contiene la parte analógica del CAD. La segunda es un microcontrolador basado en Arduino, que será la encargada de controlar la parte analógica actuando como parte digital del sistema y generando los algoritmos de conversión. La integración de ambas partes se hará a través de un diseño y fabricación de un PCB a modo de shield que se va a acoplar a la tarjeta Arduino
Open Access
A family of alternating current amplifiers for ultra-low frequency operation
(Wiley, 2021) Martincorena Arraiza, Maite; Carlosena García, Alfonso; Cruz Blas, Carlos Aristóteles de la; Beloso Legarra, Javier; López Martín, Antonio; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica, Electrónica y de Comunicación; Universidad Pública de Navarra / Nafarroako Unibertsitate Publikoa
A family of capacitively coupled alternating current (AC) amplifiers featuring ultra-low (below 1 Hz) corner frequency is presented. This is achieved by using high-gain devices which actively boost feedback resistance and thus reduce corner frequency. This procedure is often termed, though with a different purpose, as 'bootstrapping'. The proposed architectures are very general and admit several possible practical implementations. To demonstrate their usefulness, the circuits are implemented with two operational amplifiers (OA), but other active devices such as operational transconductance amplifiers (OTAs) can be alternatively used. All circuits have been theoretically analyzed, extensively simulated and measured, exhibiting high-pass cutoff frequencies as low as 30 mHz.
Open Access
Gain-boosted super class AB OTAs based on nested local feedback
(IEEE, 2021) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Ramírez-Angulo, Jaime; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Institute of Smart Cities - ISC; Ingeniería Eléctrica y Electrónica
A new approach to design super class AB operational transcon-ductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOML) of 236 V-1. To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.
Open Access
Two-stage OTA with all subthreshold MOSFETs and optimum GBW to DC-current ratio
(IEEE, 2022) Beloso Legarra, Javier; Grasso, A.; López Martín, Antonio; Palumbo, Gaetano; Pennisi, Salvatore; Institute of Smart Cities - ISC
An approach for the design of two-stage classAB OTAs with sub-1µA current consumption is proposed and demonstrated. The approach employs MOS transistors operating in subthreshold and allows maximum gain-bandwidth product (GBW) to be achieved for a given DC current budget, by setting optimum distribution of DC currents in the two amplifier stages. Following this strategy, a class AB OTA was designed in a standard 0.5-µm CMOS technology supplied from 1.6-V and experimentally tested. Measured GBW was 307 kHz with 980-nA DC current consumption while driving an output capacitance of 40 pF with an average slew rate of 96 V/ms
Open Access
Design of low power sub-threshold two-stage CMOS OTAs using different compensation techniques
(2018) Beloso Legarra, Javier; Grasso, Dario; López Martín, Antonio; Escuela Técnica Superior de Ingenieros Industriales y de Telecomunicación; Telekomunikazio eta Industria Ingeniarien Goi Mailako Eskola Teknikoa; Università degli Studi di Catania (Italia)
In this current final master thesis, different compensation techniques will be studied, simulated and compared in CMOS amplifiers. Specifically, these techniques will be applied in twostage Operational Transconductance Amplifiers (OTAs). Due to the presence of both stages, the compensation techniques will be required to maintain the stability of the system. Another important aspect to consider is the inversion mode used. The circuit will be designed using the sub-threshold mode to obtain a low voltage-low power system. Using these compensation techniques with the transistors operating in the sub-threshold mode, two OTAs will be designed. One of them will be based in a Class-A amplifier, and the another in a Class-AB amplifier which uses the Quasi Floating- Gate (QFG) transistor technique. The objective is to compare them by some Figures of Merits (FOM), and relate them to different aspects of the system such as consumption, bandwidth, phase margin or slew rate. Finally, an optimal configuration will be found by these FOM.
Open Access
Power-efficient CMOS amplifiers for battery-supplied systems
(2023) Beloso Legarra, Javier; López Martín, Antonio; Cruz Blas, Carlos Aristóteles de la; Ingeniería Eléctrica, Electrónica y de Comunicación; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren
In this Thesis, the design of power-efficient CMOS amplifiers that are suitable for battery-supplied systems with low-voltage and low-power constraints is developed. This type of circuit is essential in modern portable systems as it performs several signal processing functions, thus requiring high-performance characteristics. To this end, novel circuit-level design techniques and methodologies have been proposed with the aim of improving the performance of the amplifier while preserving simultaneously a reduced power dissipation. The following contributions are focused on single-stage and two-stage amplifier architectures. In the case of single-stage topologies, a unified approach that allows analyzing simultaneously in a common framework the most common single-stage amplifiers for a fixed current budget has been proposed, with the addition of the latest device and circuit level techniques. The design of power-efficient single-stage amplifiers is expanded by proposing several topologies based on non-linear current mirrors as class-AB current boosting technique operating in weak inversion. To illustrate their applicability in switched-capacitor circuits, a sample-and-hold has been designed. All these circuits have been implemented in a 180-nm process and validated experimentally. Finally, a novel design methodology for two-stage amplifiers operating in weak inversion region that optimizes the gain-bandwidth product for a given current budget by exploiting the frequency compensation is proposed. In order to validate the proposal, several experimental measurements of a prototype implemented in a 0.5-μm process have been performed.
Open Access
Power-efficient single-stage class-AB OTA based on non-linear nested current mirrors
(IEEE, 2023) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; López Martín, Antonio; Institute of Smart Cities - ISC
A novel approach to design low-power area-efficient rail-to-rail output single-stage class-AB operational transconductance amplifiers (OTAs) with enhanced large- and small-signal performance to drive large capacitive loads is presented. It is based on a non-linear nested current mirror at the active load of a splitted differential input pair biased in weak inversion that boosts dynamic currents beyond their quiescent value directly at the output branch. As a result, slew rate, DC gain, gainbandwidth product, settling time and noise performance are improved without additional circuit elements or power consumption. An OTA prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of 2.9 µW from a supply voltage of ±0.5 V and a silicon area of 0.001 mm2 . Measurement results validate the advantages of the proposal, exhibiting positive and negative slew rates of 110 V/ms and −58 V/ms, respectively, and a gain-bandwidth product of 136 kHz with a phase margin of 90◦ for a capacitive load of 160 pF.
Open Access
Very-low frequency capacitively coupled AC amplifier with a current feedback operational amplifier
(Wiley, 2023) Beloso Legarra, Javier; Cruz Blas, Carlos Aristóteles de la; Carlosena García, Alfonso; Martincorena Arraiza, Maite; Ingeniería Eléctrica, Electrónica y de Comunicación; Institute of Smart Cities - ISC; Ingeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzaren; Universidad Pública de Navarra / Nafarroako Unibertsitate Publikoa
In this paper, we propose the idea of using transimpedance amplifiers, in lieu of operational amplifiers (OAs) or transconductance amplifiers (OTAs) to design capacitively coupled AC amplifiers. The idea is demonstrated with a current feedback operational amplifier (CFOA) as an active element, which is actually an architecture consisting of voltage buffers and current copiers (mirrors). This last characteristic is further exploited to make the corner frequency of the AC amplifier tunable by means of bootstrapping low-valued resistors with the output buffer. It is particularly suited to achieve very-low corner frequencies as needed in applications such as bio- or seismic signals. The idea is demonstrated with simulations and experimental results with a discrete implementation.