Low-voltage CMOS bulk-driven buffer with bootstrapping technique for gain enhancement and THD-noise reduction

dc.contributor.authorCruz Blas, Carlos Aristóteles de la
dc.contributor.authorCarrillo, Juan M.
dc.contributor.departmentIngeniería Eléctrica, Electrónica y de Comunicaciónes_ES
dc.contributor.departmentInstitute of Smart Cities - ISCen
dc.contributor.departmentIngeniaritza Elektrikoa, Elektronikoaren eta Telekomunikazio Ingeniaritzareneu
dc.date.accessioned2023-05-15T13:48:28Z
dc.date.available2023-05-15T13:48:28Z
dc.date.issued2022
dc.date.updated2023-05-15T13:41:32Z
dc.description.abstractIn this paper, a bootstrapping technique is applied to a bulk-driven voltage buffer for canceling the gate-source transconductance in order to improve the cell gain, the linearity and reduce the input-referred noise. The bootstrapped circuitry is conveniently implemented by only using a capacitor and a pseudo resistor. The suitability of the technique is demonstrated by simulation results using a flipped voltage follower, even though it is general and can be applied to other structures. A 1-V buffer is designed in 0.18 µm CMOS technology, showing a 4.3 times improvement in the voltage gain (conventional 0.21 V/V, bootstrapped 0.90 V/V), increasing 5 times the input voltage range for a 1% THD (conventional 50 mV, bootstrapped 250 mV) and reducing the input equivalent noise around a 16% (conventional 180 nV/-√Hz, bootstrapped 155 nV/√Hz at 10 kHz).en
dc.description.sponsorshipThis work has been funded by projects RTI2018-095994-B-I00 and PID2019-107258RB-C32 from MCIN/AEI/10.13039/501100011033, and by Fondo Europeo de Desarrollo Regional (FEDER).en
dc.format.mimetypeapplication/pdfen
dc.identifier.citationDe-La-Cruz-Blas, C. A., Carrillo, J. M. (2022) Low-voltage CMOS bulk-driven buffer with bootstrapping technique for gain enhancement and THD-noise reduction. En Conference on Design of Circuits and Integrated Systems, DCIS 2022: proceedings of the 37th Conference on Design of Circuits and Integrated Systems (pp. 248-251). IEEE. https://doi.org/10.1109/DCIS55711.2022.9970114.en
dc.identifier.doi10.1109/DCIS55711.2022.9970114
dc.identifier.isbn978-1-6654-5950-1
dc.identifier.urihttps://academica-e.unavarra.es/handle/2454/45267
dc.language.isoengen
dc.publisherIEEEen
dc.relation.ispartof2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), p.248-251, ISBN 978-1-6654-5950-1en
dc.relation.projectIDinfo:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/RTI2018-095994-B-I00/ES/
dc.relation.projectIDinfo:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107258RB-C32/ES/
dc.relation.publisherversionhttps://doi.org/10.1109/DCIS55711.2022.9970114
dc.rights© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work.en
dc.rights.accessRightsinfo:eu-repo/semantics/openAccess
dc.subjectBootstrappingen
dc.subjectBulk-drivenen
dc.subjectLinearized transconductoren
dc.subjectQuasi-floating gatesen
dc.titleLow-voltage CMOS bulk-driven buffer with bootstrapping technique for gain enhancement and THD-noise reductionen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.type.versioninfo:eu-repo/semantics/acceptedVersion
dspace.entity.typePublication
relation.isAuthorOfPublication0f463668-5e83-4f16-9712-1dbcbeb46735
relation.isAuthorOfPublication.latestForDiscovery0f463668-5e83-4f16-9712-1dbcbeb46735

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