Low-voltage CMOS bulk-driven buffer with bootstrapping technique for gain enhancement and THD-noise reduction
Fecha
2022Versión
Acceso abierto / Sarbide irekia
Tipo
Contribución a congreso / Biltzarrerako ekarpena
Versión
Versión aceptada / Onetsi den bertsioa
Identificador del proyecto
Impacto
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10.1109/DCIS55711.2022.9970114
Resumen
In this paper, a bootstrapping technique is applied to a bulk-driven voltage buffer for canceling the gate-source transconductance in order to improve the cell gain, the linearity and reduce the input-referred noise. The bootstrapped circuitry is conveniently implemented by only using a capacitor and a pseudo resistor. The suitability of the technique is demonstrated by simulation results using a ...
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In this paper, a bootstrapping technique is applied to a bulk-driven voltage buffer for canceling the gate-source transconductance in order to improve the cell gain, the linearity and reduce the input-referred noise. The bootstrapped circuitry is conveniently implemented by only using a capacitor and a pseudo resistor. The suitability of the technique is demonstrated by simulation results using a flipped voltage follower, even though it is general and can be applied to other structures. A 1-V buffer is designed in 0.18 µm CMOS technology, showing a 4.3 times improvement in the voltage gain (conventional 0.21 V/V, bootstrapped 0.90 V/V), increasing 5 times the input voltage range for a 1% THD (conventional 50 mV, bootstrapped 250 mV) and reducing the input equivalent noise around a 16% (conventional 180 nV/-√Hz, bootstrapped 155 nV/√Hz at 10 kHz). [--]
Materias
Bootstrapping,
Bulk-driven,
Linearized transconductor,
Quasi-floating gates
Editor
IEEE
Publicado en
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), p.248-251, ISBN 978-1-6654-5950-1
Departamento
Universidad Pública de Navarra. Departamento de Ingeniería Eléctrica, Electrónica y de Comunicación /
Nafarroako Unibertsitate Publikoa. Ingeniaritza Elektrikoa, Elektronikoa eta Telekomunikazio Ingeniaritza Saila /
Universidad Pública de Navarra/Nafarroako Unibertsitate Publikoa. Institute of Smart Cities - ISC
Versión del editor
Entidades Financiadoras
This work has been funded by projects RTI2018-095994-B-I00 and PID2019-107258RB-C32 from MCIN/AEI/10.13039/501100011033, and by Fondo Europeo de Desarrollo Regional (FEDER).